/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 * 
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */


import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;

namespace tmpl {
    namespace dataflow_neuro {
// Circuit for storing registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word 
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
//        - the first bit is write/read_B
//        - the next lognw bits describe the location, 
//        - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
    bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
    pint nw = 1<<lognw;
    //Validation of the input 
    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
    sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
    // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
    INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
    // Sending back to the ackowledge
    delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
    //Reset Buffers
    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
    sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
    // Creating the different flip flop arrays
    bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
    andtree<lognw> atree[nw];
    AND2_X1 and_encoder[nw];
    sigbuf<wl> clock_buffer[nw];
    DFFQ_R_X1 ff[nw*wl];
    pint bitval;
    (k:nw:atree[k].supply = supply;)
    (word_idx:nw:
        // Decoding the bit pattern to understand which word we are looking at
        (pin_idx:lognw:
            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
            [bitval = 1 -> 
                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
            [] bitval = 0 ->
                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
            []bitval >= 2 -> {false : "fuck"};
            ]
        )
        // Activating the fake clock for the right word
        atree[word_idx].out = _out_encoder[word_idx];    
        and_encoder[word_idx].a = _out_encoder[word_idx];
        and_encoder[word_idx].b = _clock;
        and_encoder[word_idx].y = _clock_word_temp[word_idx];
        and_encoder[word_idx].vdd = supply.vdd;
        and_encoder[word_idx].vss = supply.vss;
        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
        clock_buffer[word_idx].supply = supply;
        // Describing all the FF and their connection
        (bit_idx:wl:
            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
        )
    )
    }

// Circuit for storing  and reading registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word 
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
//        - the MSB is write/read_B
//        - the next MSB bits (size lognw) are the location, 
//        - the LSB (size wl) are the word to write
// out -> in case a reading phase is required, the output is used to show the stored data
//        - the MSB bits (size lognw) tell the read register
//        - the LSB bits (size wl) tell the word read
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
    pint nw = 1<<lognw;
    bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
    //Validation of the input 
    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
    sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
    // Acknowledgment
    OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
    sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
    // WRITE
        // Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
        bool _in_v_temp_write;
        AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
        delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
        INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
        sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
        sigbuf<wl> clock_buffer[nw];
        bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
        // Sending back to the acknowledge
        bool _in_a_write_temp;
        delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
        AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
    // READ
        //Outputing the word to read
        AND2_X1 word_to_read[nw];
        sigbuf<wl*2> word_to_read_X[nw];
        ortree<nw> bitselector_t[wl];
        ortree<nw> bitselector_f[wl];
        AND2_X1 word_selector_t[nw*wl];
        AND2_X1 word_selector_f[nw*wl];
        buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
        AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
        // Outputting the address if the read is true
        (i:lognw:
            address_propagator_t[i].a = in.d.d[lognw+wl].t;
            address_propagator_t[i].b = in.d.d[i+wl].t;
            address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
            address_propagator_t[i].vdd = supply.vdd;
            address_propagator_t[i].vss = supply.vss;
            
            address_propagator_f[i].a = in.d.d[lognw+wl].t;
            address_propagator_f[i].b = in.d.d[i+wl].f;
            address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
            address_propagator_f[i].vdd = supply.vdd;
            address_propagator_f[i].vss = supply.vss;
        )
        AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
    //Reset Buffers
    bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
    sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
    sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);

    //Creating the encoder
    andtree<lognw> atree[nw];
    OR2_X1 or_encoder[nw];
    INV_X1 inv_encoder[nw];
    // Creating the different flip flop arrays
    bool _out_encoder[nw];
    DFFQ_R_X1 ff[nw*wl];
    AND2_X1 val_chck[nw*wl];
    bool _val_chck_out[nw*wl];
    bool _in_v_temp_buf[nw*wl];
    sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
    
    // For loop for assigning the different components
    pint bitval;
    (k:nw:atree[k].supply = supply;)
    (word_idx:nw:
        // Decoding the bit pattern to understand which word we are looking at
        (pin_idx:lognw:
            bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
            [bitval = 1 -> 
                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
            [] bitval = 0 ->
                atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
            []bitval >= 2 -> {false : "fuck"};
            ]
        )
        // WRITE: Activating the fake clock for the right word
        atree[word_idx].out = _out_encoder[word_idx];    
        inv_encoder[word_idx].a = _out_encoder[word_idx];
        inv_encoder[word_idx].y = or_encoder[word_idx].a;
        inv_encoder[word_idx].vdd = supply.vdd;
        inv_encoder[word_idx].vss = supply.vss;
        or_encoder[word_idx].b = _clock[word_idx];
        or_encoder[word_idx].y = _clock_word_temp[word_idx];
        or_encoder[word_idx].vdd = supply.vdd;
        or_encoder[word_idx].vss = supply.vss;
        clock_buffer[word_idx].in = _clock_word_temp[word_idx];
        clock_buffer[word_idx].supply = supply;
        // READ: Selecting the right word to read if read is high
        word_to_read[word_idx].a = in.d.d[lognw+wl].t;
        word_to_read[word_idx].b = _out_encoder[word_idx];
        word_to_read[word_idx].y = word_to_read_X[word_idx].in;
        word_to_read[word_idx].vdd = supply.vdd;
        word_to_read[word_idx].vss = supply.vss;
        word_to_read_X[word_idx].supply = supply;

        
        (bit_idx:wl:
            // Describing all the FF and their connection
            val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
            val_chck[bit_idx].b = in.d.d[bit_idx].t;
            val_chck[bit_idx].y = _val_chck_out[bit_idx];
            val_chck[bit_idx].vdd = supply.vdd;
            val_chck[bit_idx].vss = supply.vss;
            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
            // READ: creating the selectors for propagating the right word
            word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
            word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
            word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
            word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
            word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
            word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
            bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
            bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
            bitselector_t[bit_idx].supply = supply;
            bitselector_f[bit_idx].supply = supply;
        )
    )
    }


}}

