diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index b8a7ffb..4dd5abe 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -587,4 +587,63 @@ namespace tmpl { BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); } + + // Programmable delay line. + // N is the number of layers, + // the longest layer having 2**N DLY elements + export template + defproc delayprog (bool! y; bool? a, s[N]; power supply) + { + + { N >= 0 : "What?" }; + { N < 9 : "Delay prog size is given in 2**N. Given N is too big." }; + + + AND2_X1 and2[N]; + MUX2_X1 mu2[N]; + DLY4_X1 dly[(1<"t.dp.and2[0]._y"- +~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+ +"t.dp.and2[0]._y"->"t.dp.and2[0].y"- +~("t.dp.and2[0]._y")->"t.dp.and2[0].y"+ +"t.dp.and2[1].a"&"t.dp.and2[1].b"->"t.dp.and2[1]._y"- +~("t.dp.and2[1].a"&"t.dp.and2[1].b")->"t.dp.and2[1]._y"+ +"t.dp.and2[1]._y"->"t.dp.and2[1].y"- +~("t.dp.and2[1]._y")->"t.dp.and2[1].y"+ +"t.dp.and2[2].a"&"t.dp.and2[2].b"->"t.dp.and2[2]._y"- +~("t.dp.and2[2].a"&"t.dp.and2[2].b")->"t.dp.and2[2]._y"+ +"t.dp.and2[2]._y"->"t.dp.and2[2].y"- +~("t.dp.and2[2]._y")->"t.dp.and2[2].y"+ +"t.dp.and2[3].a"&"t.dp.and2[3].b"->"t.dp.and2[3]._y"- +~("t.dp.and2[3].a"&"t.dp.and2[3].b")->"t.dp.and2[3]._y"+ +"t.dp.and2[3]._y"->"t.dp.and2[3].y"- +~("t.dp.and2[3]._y")->"t.dp.and2[3].y"+ += "t.dp.s[0]" "t.dp.mu2[0].s" += "t.dp.s[0]" "t.dp.and2[0].b" += "t.dp.s[1]" "t.dp.mu2[1].s" += "t.dp.s[1]" "t.dp.and2[1].b" += "t.dp.s[2]" "t.dp.mu2[2].s" += "t.dp.s[2]" "t.dp.and2[2].b" += "t.dp.s[3]" "t.dp.mu2[3].s" += "t.dp.s[3]" "t.dp.and2[3].b" += "t.dp.supply.vdd" "t.dp.dly[14].vdd" += "t.dp.supply.vdd" "t.dp.dly[13].vdd" += "t.dp.supply.vdd" "t.dp.dly[12].vdd" += "t.dp.supply.vdd" "t.dp.dly[11].vdd" += "t.dp.supply.vdd" "t.dp.dly[10].vdd" += "t.dp.supply.vdd" "t.dp.dly[9].vdd" += "t.dp.supply.vdd" "t.dp.dly[8].vdd" += "t.dp.supply.vdd" "t.dp.dly[7].vdd" += "t.dp.supply.vdd" "t.dp.dly[6].vdd" += "t.dp.supply.vdd" "t.dp.dly[5].vdd" += "t.dp.supply.vdd" "t.dp.dly[4].vdd" += "t.dp.supply.vdd" "t.dp.dly[3].vdd" += "t.dp.supply.vdd" "t.dp.dly[2].vdd" += "t.dp.supply.vdd" "t.dp.dly[1].vdd" += "t.dp.supply.vdd" "t.dp.dly[0].vdd" += "t.dp.supply.vdd" "t.dp.mu2[3].vdd" += "t.dp.supply.vdd" "t.dp.mu2[2].vdd" += "t.dp.supply.vdd" "t.dp.mu2[1].vdd" += "t.dp.supply.vdd" "t.dp.mu2[0].vdd" += "t.dp.supply.vdd" "t.dp.and2[3].vdd" += "t.dp.supply.vdd" "t.dp.and2[2].vdd" += "t.dp.supply.vdd" "t.dp.and2[1].vdd" += "t.dp.supply.vdd" "t.dp.and2[0].vdd" += "t.dp.supply.vss" "t.dp.dly[14].vss" += "t.dp.supply.vss" "t.dp.dly[13].vss" += "t.dp.supply.vss" "t.dp.dly[12].vss" += "t.dp.supply.vss" "t.dp.dly[11].vss" += "t.dp.supply.vss" "t.dp.dly[10].vss" += "t.dp.supply.vss" "t.dp.dly[9].vss" += "t.dp.supply.vss" "t.dp.dly[8].vss" += "t.dp.supply.vss" "t.dp.dly[7].vss" += "t.dp.supply.vss" "t.dp.dly[6].vss" += "t.dp.supply.vss" "t.dp.dly[5].vss" += "t.dp.supply.vss" "t.dp.dly[4].vss" += "t.dp.supply.vss" "t.dp.dly[3].vss" += "t.dp.supply.vss" "t.dp.dly[2].vss" += "t.dp.supply.vss" "t.dp.dly[1].vss" += "t.dp.supply.vss" "t.dp.dly[0].vss" += "t.dp.supply.vss" "t.dp.mu2[3].vss" += "t.dp.supply.vss" "t.dp.mu2[2].vss" += "t.dp.supply.vss" "t.dp.mu2[1].vss" += "t.dp.supply.vss" "t.dp.mu2[0].vss" += "t.dp.supply.vss" "t.dp.and2[3].vss" += "t.dp.supply.vss" "t.dp.and2[2].vss" += "t.dp.supply.vss" "t.dp.and2[1].vss" += "t.dp.supply.vss" "t.dp.and2[0].vss" +"t.dp.mu2[0].s"->"t.dp.mu2[0]._s"- +~("t.dp.mu2[0].s")->"t.dp.mu2[0]._s"+ +~"t.dp.mu2[0].a"&~"t.dp.mu2[0].s"|~"t.dp.mu2[0].b"&~"t.dp.mu2[0]._s"->"t.dp.mu2[0]._y"+ +"t.dp.mu2[0].a"&"t.dp.mu2[0]._s"|"t.dp.mu2[0].b"&"t.dp.mu2[0].s"->"t.dp.mu2[0]._y"- +"t.dp.mu2[0]._y"->"t.dp.mu2[0].y"- +~("t.dp.mu2[0]._y")->"t.dp.mu2[0].y"+ +"t.dp.mu2[1].s"->"t.dp.mu2[1]._s"- +~("t.dp.mu2[1].s")->"t.dp.mu2[1]._s"+ +~"t.dp.mu2[1].a"&~"t.dp.mu2[1].s"|~"t.dp.mu2[1].b"&~"t.dp.mu2[1]._s"->"t.dp.mu2[1]._y"+ +"t.dp.mu2[1].a"&"t.dp.mu2[1]._s"|"t.dp.mu2[1].b"&"t.dp.mu2[1].s"->"t.dp.mu2[1]._y"- +"t.dp.mu2[1]._y"->"t.dp.mu2[1].y"- +~("t.dp.mu2[1]._y")->"t.dp.mu2[1].y"+ +"t.dp.mu2[2].s"->"t.dp.mu2[2]._s"- +~("t.dp.mu2[2].s")->"t.dp.mu2[2]._s"+ +~"t.dp.mu2[2].a"&~"t.dp.mu2[2].s"|~"t.dp.mu2[2].b"&~"t.dp.mu2[2]._s"->"t.dp.mu2[2]._y"+ +"t.dp.mu2[2].a"&"t.dp.mu2[2]._s"|"t.dp.mu2[2].b"&"t.dp.mu2[2].s"->"t.dp.mu2[2]._y"- +"t.dp.mu2[2]._y"->"t.dp.mu2[2].y"- +~("t.dp.mu2[2]._y")->"t.dp.mu2[2].y"+ +"t.dp.mu2[3].s"->"t.dp.mu2[3]._s"- +~("t.dp.mu2[3].s")->"t.dp.mu2[3]._s"+ +~"t.dp.mu2[3].a"&~"t.dp.mu2[3].s"|~"t.dp.mu2[3].b"&~"t.dp.mu2[3]._s"->"t.dp.mu2[3]._y"+ +"t.dp.mu2[3].a"&"t.dp.mu2[3]._s"|"t.dp.mu2[3].b"&"t.dp.mu2[3].s"->"t.dp.mu2[3]._y"- +"t.dp.mu2[3]._y"->"t.dp.mu2[3].y"- +~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+ +"t.dp.dly[0].a"->"t.dp.dly[0]._y"- +~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+ +"t.dp.dly[0]._y"->"t.dp.dly[0].y"- +~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+ +"t.dp.dly[1].a"->"t.dp.dly[1]._y"- +~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+ +"t.dp.dly[1]._y"->"t.dp.dly[1].y"- +~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+ +"t.dp.dly[2].a"->"t.dp.dly[2]._y"- +~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+ +"t.dp.dly[2]._y"->"t.dp.dly[2].y"- +~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+ +"t.dp.dly[3].a"->"t.dp.dly[3]._y"- +~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+ +"t.dp.dly[3]._y"->"t.dp.dly[3].y"- +~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+ +"t.dp.dly[4].a"->"t.dp.dly[4]._y"- +~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+ +"t.dp.dly[4]._y"->"t.dp.dly[4].y"- +~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+ +"t.dp.dly[5].a"->"t.dp.dly[5]._y"- +~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+ +"t.dp.dly[5]._y"->"t.dp.dly[5].y"- +~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+ +"t.dp.dly[6].a"->"t.dp.dly[6]._y"- +~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+ +"t.dp.dly[6]._y"->"t.dp.dly[6].y"- +~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+ +"t.dp.dly[7].a"->"t.dp.dly[7]._y"- +~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+ +"t.dp.dly[7]._y"->"t.dp.dly[7].y"- +~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+ +"t.dp.dly[8].a"->"t.dp.dly[8]._y"- +~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+ +"t.dp.dly[8]._y"->"t.dp.dly[8].y"- +~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+ +"t.dp.dly[9].a"->"t.dp.dly[9]._y"- +~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+ +"t.dp.dly[9]._y"->"t.dp.dly[9].y"- +~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+ +"t.dp.dly[10].a"->"t.dp.dly[10]._y"- +~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+ +"t.dp.dly[10]._y"->"t.dp.dly[10].y"- +~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+ +"t.dp.dly[11].a"->"t.dp.dly[11]._y"- +~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+ +"t.dp.dly[11]._y"->"t.dp.dly[11].y"- +~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+ +"t.dp.dly[12].a"->"t.dp.dly[12]._y"- +~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+ +"t.dp.dly[12]._y"->"t.dp.dly[12].y"- +~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+ +"t.dp.dly[13].a"->"t.dp.dly[13]._y"- +~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+ +"t.dp.dly[13]._y"->"t.dp.dly[13].y"- +~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+ +"t.dp.dly[14].a"->"t.dp.dly[14]._y"- +~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+ +"t.dp.dly[14]._y"->"t.dp.dly[14].y"- +~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+ += "t.dp.dly[6].y" "t.dp.mu2[3].b" += "t.dp.dly[6].a" "t.dp.dly[5].y" += "t.dp.dly[5].a" "t.dp.dly[4].y" += "t.dp.dly[4].a" "t.dp.and2[3].y" += "t.dp.dly[3].y" "t.dp.mu2[2].b" += "t.dp.dly[3].a" "t.dp.dly[2].y" += "t.dp.dly[2].a" "t.dp.and2[2].y" += "t.dp.dly[1].y" "t.dp.mu2[1].b" += "t.dp.dly[1].a" "t.dp.and2[1].y" += "t.dp.dly[0].y" "t.dp.mu2[0].b" += "t.dp.dly[0].a" "t.dp.and2[0].y" += "t.dp._a[1]" "t.dp.mu2[1].a" += "t.dp._a[1]" "t.dp.and2[1].a" += "t.dp._a[1]" "t.dp.mu2[0].y" += "t.dp._a[2]" "t.dp.mu2[2].a" += "t.dp._a[2]" "t.dp.and2[2].a" += "t.dp._a[2]" "t.dp.mu2[1].y" += "t.dp._a[3]" "t.dp.mu2[3].a" += "t.dp._a[3]" "t.dp.and2[3].a" += "t.dp._a[3]" "t.dp.mu2[2].y" += "t.dp.y" "t.dp.mu2[3].y" += "t.dp.y" "t.dp._a[4]" += "Vdd" "t.dp.supply.vdd" += "GND" "t.dp.supply.vss" += "t.s[0]" "t.dp.s[0]" += "t.s[1]" "t.dp.s[1]" += "t.s[2]" "t.dp.s[2]" += "t.s[3]" "t.dp.s[3]" diff --git a/test/unit_tests/delayprog_4/test.act b/test/unit_tests/delayprog_4/test.act new file mode 100644 index 0000000..ab4e929 --- /dev/null +++ b/test/unit_tests/delayprog_4/test.act @@ -0,0 +1,41 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/primitives.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc delayprog_4 (bool? s[4], a; bool! y){ + delayprog<4> dp(.a=a, .y=y, .s = s); + dp.supply.vss = GND; + dp.supply.vdd = Vdd; + +} + +delayprog_4 t; \ No newline at end of file diff --git a/test/unit_tests/delayprog_4/test.prsim b/test/unit_tests/delayprog_4/test.prsim new file mode 100644 index 0000000..02e71b6 --- /dev/null +++ b/test/unit_tests/delayprog_4/test.prsim @@ -0,0 +1,42 @@ +watchall + +system "echo '0'" + +set t.a 0 +set t.s[0] 1 +set t.s[1] 1 +set t.s[2] 1 +set t.s[3] 1 + +cycle +mode run + +assert t.y 0 + +system "echo '[] setting high'" +set t.a 1 +cycle +assert t.y 1 + +system "echo '[] setting low'" +set t.a 0 +cycle +assert t.y 0 + +system "echo '[] setting configs low'" +set t.s[0] 0 +set t.s[1] 0 +set t.s[2] 0 +set t.s[3] 0 +cycle +assert t.y 0 + +system "echo '[] setting high'" +set t.a 1 +cycle +assert t.y 1 + +system "echo '[] setting low'" +set t.a 0 +cycle +assert t.y 0