From 00869fc16eb4179ab3b781a326c8eb8704b4ed1e Mon Sep 17 00:00:00 2001 From: alexmadison Date: Tue, 1 Mar 2022 15:26:43 +0100 Subject: [PATCH 1/3] programmable delay tested --- dataflow_neuro/primitives.act | 59 +++++++ test/unit_tests/delayprog_4/run/prsim.out | 134 +++++++++++++++ test/unit_tests/delayprog_4/run/prsim.pdf | Bin 0 -> 44304 bytes test/unit_tests/delayprog_4/run/test.prs | 190 ++++++++++++++++++++++ test/unit_tests/delayprog_4/test.act | 41 +++++ test/unit_tests/delayprog_4/test.prsim | 42 +++++ 6 files changed, 466 insertions(+) create mode 100644 test/unit_tests/delayprog_4/run/prsim.out create mode 100644 test/unit_tests/delayprog_4/run/prsim.pdf create mode 100644 test/unit_tests/delayprog_4/run/test.prs create mode 100644 test/unit_tests/delayprog_4/test.act create mode 100644 test/unit_tests/delayprog_4/test.prsim diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index b8a7ffb..4dd5abe 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -587,4 +587,63 @@ namespace tmpl { BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); } + + // Programmable delay line. + // N is the number of layers, + // the longest layer having 2**N DLY elements + export template + defproc delayprog (bool! y; bool? a, s[N]; power supply) + { + + { N >= 0 : "What?" }; + { N < 9 : "Delay prog size is given in 2**N. Given N is too big." }; + + + AND2_X1 and2[N]; + MUX2_X1 mu2[N]; + DLY4_X1 dly[(1<D=92^|oTwx|)@)9s877nmGfqx2QTpZn< zD4v%op+UhWY2jgGW}z+vGYz}bbOAcJIssiQ9L&7`xAK3_!wj)0S(w`Z#T~t1dY_GP za`LdVa&hyrb8_%;32;ydu=B8Tb8>R=a&vI8b3dC_eb(gm&ygr>>K3k!?k;99&px~E z|Ml#%v;PmbKBN5KGNf(nV4kC3leUAoR?@=E(Hs^DMGFTjH){%x=YXj{3%a_wSOD!& zyt2pq6ed{Ooqs<(M2RQ@Y)&5u^qnZFxrAPFvZI0c6RT;mnP@uW5dYj)X+8RlF&=N* zNI5r~LiAVl4h;>N>!U9zqMt6?*`6*zBR~AZ|2*BC)fhv%$UFHT4hGrYnm6}r8oau> z<~u(*K1&skpeg8C40xJJW9zy->oO9t`>_TzHoLCL{=TpN?Y=7*iNV;2=VGi`(}$H% z^Uv)<&7ae|#{;VXL|XrsbX}l;0EAoP4*#o#uBU}n|HsSKr}dqhns-4hue+CjGDP;B z{l4~lJiToAvu_;m7{0LTdz-cJ2h|Z{eL7}s)wuHp!iVqYaH-|9=;B#UC;P>#lC`hQ znY>rqmeEE=sBa#AvL#eqVf_6;svn$6O^tCx$eg-tyZy=~%C@g;)=6Cov-R~*IP%el zv4VLDZj25=BvGi>Cx+pAxCqi;<)u^~2Y)+1xhiY4(FSVyl7_t|JLLK6W9 z%MvOp!bcpw-?nzqEmprTxnBLQhvVm0lpJZO*_Dg0&U!+hm6zC%@Cd0-JvRZx4Vx^* ztWAk=tync|Fm)y6t#T57{LOAa0c9j1M^k~ABY>mhX&8U$T-0ppBZrO2xZx&N?vmcv z>rE0(s(BDOP2BuJcLGy-DNsy-@$~m|FwJs9!RN$F3d1*q*4Dxy(FE!~gu@n07{W9o z(*3(8)p%GaZqL0dK&-C>)L-*6P?BjXzp zg|RBP1cNcdjWRGWR24wod0%JD!_#@NeH3v9ZC_}e4Cv;KM&FkJ%i<{aIJ(4p8Yk>^ zqD)K_${|7vUS&Yg;KF^}_v2f!H}(ty_(Ah5O^pHma4rgOhyojzw{5ou}uvLyW%g-0f zom`k7n}Luw6wNu%!^h6?S=)gCk{V2n30oO26$nag?@Cpv&|@(d8HVM@qtLk+qilG> zDnfiZCM*a28aM=NPhQ%m1)tVJQO98xCzm)^q1Uq3;=S%~dx59%Nec5fF7X0- z;F#ysOUVxxD+w;EE$Q#SzUT&`kYZ|V-R>`aHr4t`xLP;K?sbqJyjRS?$J|9)!EVD! zl)8_>!eB?A8f4aLhrwKV%u|M2W~^hRPXJGYZXJPT#&WeM&NI3~G@K#dBC(<5yE$fN zl4!9c_Nm{fd`}aJMX;~n^sTUz9C@fz8EB5IfRk0V#?k)3jJF4Sw{NQs9)uZrlvY|FTZeVGrq#wkEIu7 z{}u3lO6x(Wqu|^6<7LP|(8f&Y?fQm-MhP#R#9JcKeDBFZl7>kF1NiXNvE=L?q&Jo}?J1Mz=>Zk8e>lyD-V=|{5>4p=0slF@0WKLZFvRP}CQ=rvjd zOexSTGF2yWSI*$3dUdghLU-N@cZ-t>>oGOoLavcYfA1mBn$Miu^OzZUFC^bn2me9>{INcg7T zDz}aV2NNr9ebxj*SwCU~A}BKwPz|%|Wn3313qw{6%DrO9*BfX)`mptR>Nh+JD}Qq% zI{<~~LKs*!C8VkXQrXfCx1|To9I5KCTe6UMuhAnA;YEGShk#n`e9F{VFkl3?8I~B$ z#1x^A`pEOSBHX8Cf_5-Ai39Yz23^ryU;B_Ae=nJs8S@kq2g4JivQPymQ+J0zFfEx? zS{-0PU@suXqn1YZ^Tntc&q(7vr8JpKNsCE&F(W-%(KH>7u~|rB896mZw$G^hD{1Vo zVN`)D>(;;Lq$a=9(9_oAcrx<}db7V6^&`xj$ zM_o{Y{5lyy$tj)oG@0Tb?uudpW4$}mn6=~q7xMv%Z#Ud=qn=>0reL8!G~6frqsxnkHJR7W=6 zcSU9AN1wvqbDPnN2skpBJxyvHbCJVU7J9u3`$+GA$+KvWiEF!A;6x)Lr6;F<3LJm| zmR7q|jlEfXXmJ#^%%s+}RQL6EYtp8Jlh$P=(06_Vh~enIn|7sp1?Qw@7aUAp1`tzV zt7o;)S2KB$1Sm&_jEJ5XCVu?;=GZ%0OfAP67= z`i^vkHiLUyY(+46ff@HgyAg$@Jk%LRXQ?_~c8lDwl`y?unZ+@01CfHtfw$f1ko$s= z{8j)F$+iWD$ZT0^c>lZNQU)eDCee#p`jR<<3XHfl(F`KKamh#)0exd+1>=*^_dwd| zg@bi6`s`ew%bQ-@MyXro$SWfhiHRZC$004jvDyy@(5^tFYMs_2|BvC{wlnjg2!unt z^x8}@wrAwr7$jF|*mGv|W*jcNwoSh8ZQOoVqoVh_iy0fBKUw(bb|WGDGS(+SdW97; zf;if1M;XL;pSn;f)F&b$uh;ktt1|dLs@xN1 zuiXC(IOUDS-j|pHtr_T~7l2VtBA@G`T4hO2O2YG@>*+cbion-OQX~Sp?9fM2Y%)_L z{1eW1K7$H*m1!wd>|9 zkXg#CNrL>TBPffzjpp{6D7fP5Hi;XSLL}xvjYA#ZiNfQ$#JQa9!JtlC7%8 z^XUNQXkiWvZBu_jSb0{JV)!6>mdakQxBbPmjh%T{K49+{NFa|on)XqTgq}gt32vrw zxs(ITOKLxrU2toyAuR*7%E5>P9@Ma!ZW%7|@o#YqW%^efF=55=Bdj=v+qS^+U94+@ z7>(EAjr-;m+^-uaUJiUh9ouz6`fNRf-KSiS#^y=UGi)+xz$Yw9rF^{dfk>UG$VO}> zTIlCe;C7EBli{S%t=b1olBnZNp?Utp>q7zs-ee|jgzPVtw}Ap_`_+@&Gw6mvd2Mu} zaTuod6{8)5Hon2eQnF-Mgr(I!^I|~fZ`|fg+T2L%Q)e%JeR4+O1}P@;?N*r!ma4I! z#A5cq65h{DbS`RGMGve9u&tda8SvAn<1E1eHgxMEa`@7M8_qV;hPS>R`}cH5UTqtI z)pXxSwrjLtXl07Nw}A(~DNs{ywZvscQF6+h1`C5O(aCMLXWTH_?YgGu?XrK>`vwE7 zJet1VTF^JtUC?j|et>r|6Urm4zYq}|e%;wqQQKxr%# z9TyGrlo(uWOG%s&+Xv0-S>3#`n0rgp^YsXh{-g{VSNnzNSTUW5#K_SgK7h3t*9m

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zW|-UKL?BZx==YNjkb=;$-`nHRkd526bV9&9aC;mEm|<>^!7M3IPHFWoDgIH z2L1kq1%Ui(9I$-;B^_w+FLA=Z(uObs{R=F@s9*6SEck1A!suVd7E)Lkm_2TV8H``Z zd~HiR1i=8_1fQ$3iM6eTGZ|!=retsF04ze+Y^Y8+I6%|inmv`Zmj#$Spb5pr)x_Bq TH=PIqBTzvyHZ}!~V`Tpa4}!Uz literal 0 HcmV?d00001 diff --git a/test/unit_tests/delayprog_4/run/test.prs b/test/unit_tests/delayprog_4/run/test.prs new file mode 100644 index 0000000..4167c16 --- /dev/null +++ b/test/unit_tests/delayprog_4/run/test.prs @@ -0,0 +1,190 @@ += "GND" "GND" += "Vdd" "Vdd" += "Reset" "Reset" += "t.y" "t.dp.y" += "t.a" "t.dp.a" += "t.dp.a" "t.dp.mu2[0].a" += "t.dp.a" "t.dp.and2[0].a" += "t.dp.a" "t.dp._a[0]" +"t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"- +~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+ +"t.dp.and2[0]._y"->"t.dp.and2[0].y"- +~("t.dp.and2[0]._y")->"t.dp.and2[0].y"+ +"t.dp.and2[1].a"&"t.dp.and2[1].b"->"t.dp.and2[1]._y"- +~("t.dp.and2[1].a"&"t.dp.and2[1].b")->"t.dp.and2[1]._y"+ +"t.dp.and2[1]._y"->"t.dp.and2[1].y"- +~("t.dp.and2[1]._y")->"t.dp.and2[1].y"+ +"t.dp.and2[2].a"&"t.dp.and2[2].b"->"t.dp.and2[2]._y"- +~("t.dp.and2[2].a"&"t.dp.and2[2].b")->"t.dp.and2[2]._y"+ +"t.dp.and2[2]._y"->"t.dp.and2[2].y"- +~("t.dp.and2[2]._y")->"t.dp.and2[2].y"+ +"t.dp.and2[3].a"&"t.dp.and2[3].b"->"t.dp.and2[3]._y"- +~("t.dp.and2[3].a"&"t.dp.and2[3].b")->"t.dp.and2[3]._y"+ +"t.dp.and2[3]._y"->"t.dp.and2[3].y"- +~("t.dp.and2[3]._y")->"t.dp.and2[3].y"+ += "t.dp.s[0]" "t.dp.mu2[0].s" += "t.dp.s[0]" "t.dp.and2[0].b" += "t.dp.s[1]" "t.dp.mu2[1].s" += "t.dp.s[1]" "t.dp.and2[1].b" += "t.dp.s[2]" "t.dp.mu2[2].s" += "t.dp.s[2]" "t.dp.and2[2].b" += "t.dp.s[3]" "t.dp.mu2[3].s" += "t.dp.s[3]" "t.dp.and2[3].b" += "t.dp.supply.vdd" "t.dp.dly[14].vdd" += "t.dp.supply.vdd" "t.dp.dly[13].vdd" += "t.dp.supply.vdd" "t.dp.dly[12].vdd" += "t.dp.supply.vdd" "t.dp.dly[11].vdd" += "t.dp.supply.vdd" "t.dp.dly[10].vdd" += "t.dp.supply.vdd" "t.dp.dly[9].vdd" += "t.dp.supply.vdd" "t.dp.dly[8].vdd" += "t.dp.supply.vdd" "t.dp.dly[7].vdd" += "t.dp.supply.vdd" "t.dp.dly[6].vdd" += "t.dp.supply.vdd" "t.dp.dly[5].vdd" += "t.dp.supply.vdd" "t.dp.dly[4].vdd" += "t.dp.supply.vdd" "t.dp.dly[3].vdd" += "t.dp.supply.vdd" "t.dp.dly[2].vdd" += "t.dp.supply.vdd" "t.dp.dly[1].vdd" += "t.dp.supply.vdd" "t.dp.dly[0].vdd" += "t.dp.supply.vdd" "t.dp.mu2[3].vdd" += "t.dp.supply.vdd" "t.dp.mu2[2].vdd" += "t.dp.supply.vdd" "t.dp.mu2[1].vdd" += "t.dp.supply.vdd" "t.dp.mu2[0].vdd" += "t.dp.supply.vdd" "t.dp.and2[3].vdd" += "t.dp.supply.vdd" "t.dp.and2[2].vdd" += "t.dp.supply.vdd" "t.dp.and2[1].vdd" += "t.dp.supply.vdd" "t.dp.and2[0].vdd" += "t.dp.supply.vss" "t.dp.dly[14].vss" += "t.dp.supply.vss" "t.dp.dly[13].vss" += "t.dp.supply.vss" "t.dp.dly[12].vss" += "t.dp.supply.vss" "t.dp.dly[11].vss" += "t.dp.supply.vss" "t.dp.dly[10].vss" += "t.dp.supply.vss" "t.dp.dly[9].vss" += "t.dp.supply.vss" "t.dp.dly[8].vss" += "t.dp.supply.vss" "t.dp.dly[7].vss" += "t.dp.supply.vss" "t.dp.dly[6].vss" += "t.dp.supply.vss" "t.dp.dly[5].vss" += "t.dp.supply.vss" "t.dp.dly[4].vss" += "t.dp.supply.vss" "t.dp.dly[3].vss" += "t.dp.supply.vss" "t.dp.dly[2].vss" += "t.dp.supply.vss" "t.dp.dly[1].vss" += "t.dp.supply.vss" "t.dp.dly[0].vss" += "t.dp.supply.vss" "t.dp.mu2[3].vss" += "t.dp.supply.vss" "t.dp.mu2[2].vss" += "t.dp.supply.vss" "t.dp.mu2[1].vss" += "t.dp.supply.vss" "t.dp.mu2[0].vss" += "t.dp.supply.vss" "t.dp.and2[3].vss" += "t.dp.supply.vss" "t.dp.and2[2].vss" += "t.dp.supply.vss" "t.dp.and2[1].vss" += "t.dp.supply.vss" "t.dp.and2[0].vss" +"t.dp.mu2[0].s"->"t.dp.mu2[0]._s"- +~("t.dp.mu2[0].s")->"t.dp.mu2[0]._s"+ +~"t.dp.mu2[0].a"&~"t.dp.mu2[0].s"|~"t.dp.mu2[0].b"&~"t.dp.mu2[0]._s"->"t.dp.mu2[0]._y"+ +"t.dp.mu2[0].a"&"t.dp.mu2[0]._s"|"t.dp.mu2[0].b"&"t.dp.mu2[0].s"->"t.dp.mu2[0]._y"- +"t.dp.mu2[0]._y"->"t.dp.mu2[0].y"- +~("t.dp.mu2[0]._y")->"t.dp.mu2[0].y"+ +"t.dp.mu2[1].s"->"t.dp.mu2[1]._s"- +~("t.dp.mu2[1].s")->"t.dp.mu2[1]._s"+ +~"t.dp.mu2[1].a"&~"t.dp.mu2[1].s"|~"t.dp.mu2[1].b"&~"t.dp.mu2[1]._s"->"t.dp.mu2[1]._y"+ +"t.dp.mu2[1].a"&"t.dp.mu2[1]._s"|"t.dp.mu2[1].b"&"t.dp.mu2[1].s"->"t.dp.mu2[1]._y"- +"t.dp.mu2[1]._y"->"t.dp.mu2[1].y"- +~("t.dp.mu2[1]._y")->"t.dp.mu2[1].y"+ +"t.dp.mu2[2].s"->"t.dp.mu2[2]._s"- +~("t.dp.mu2[2].s")->"t.dp.mu2[2]._s"+ +~"t.dp.mu2[2].a"&~"t.dp.mu2[2].s"|~"t.dp.mu2[2].b"&~"t.dp.mu2[2]._s"->"t.dp.mu2[2]._y"+ +"t.dp.mu2[2].a"&"t.dp.mu2[2]._s"|"t.dp.mu2[2].b"&"t.dp.mu2[2].s"->"t.dp.mu2[2]._y"- +"t.dp.mu2[2]._y"->"t.dp.mu2[2].y"- +~("t.dp.mu2[2]._y")->"t.dp.mu2[2].y"+ +"t.dp.mu2[3].s"->"t.dp.mu2[3]._s"- +~("t.dp.mu2[3].s")->"t.dp.mu2[3]._s"+ +~"t.dp.mu2[3].a"&~"t.dp.mu2[3].s"|~"t.dp.mu2[3].b"&~"t.dp.mu2[3]._s"->"t.dp.mu2[3]._y"+ +"t.dp.mu2[3].a"&"t.dp.mu2[3]._s"|"t.dp.mu2[3].b"&"t.dp.mu2[3].s"->"t.dp.mu2[3]._y"- +"t.dp.mu2[3]._y"->"t.dp.mu2[3].y"- +~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+ +"t.dp.dly[0].a"->"t.dp.dly[0]._y"- +~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+ +"t.dp.dly[0]._y"->"t.dp.dly[0].y"- +~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+ +"t.dp.dly[1].a"->"t.dp.dly[1]._y"- +~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+ +"t.dp.dly[1]._y"->"t.dp.dly[1].y"- +~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+ +"t.dp.dly[2].a"->"t.dp.dly[2]._y"- +~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+ +"t.dp.dly[2]._y"->"t.dp.dly[2].y"- +~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+ +"t.dp.dly[3].a"->"t.dp.dly[3]._y"- +~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+ +"t.dp.dly[3]._y"->"t.dp.dly[3].y"- +~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+ +"t.dp.dly[4].a"->"t.dp.dly[4]._y"- +~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+ +"t.dp.dly[4]._y"->"t.dp.dly[4].y"- +~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+ +"t.dp.dly[5].a"->"t.dp.dly[5]._y"- +~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+ +"t.dp.dly[5]._y"->"t.dp.dly[5].y"- +~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+ +"t.dp.dly[6].a"->"t.dp.dly[6]._y"- +~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+ +"t.dp.dly[6]._y"->"t.dp.dly[6].y"- +~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+ +"t.dp.dly[7].a"->"t.dp.dly[7]._y"- +~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+ +"t.dp.dly[7]._y"->"t.dp.dly[7].y"- +~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+ +"t.dp.dly[8].a"->"t.dp.dly[8]._y"- +~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+ +"t.dp.dly[8]._y"->"t.dp.dly[8].y"- +~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+ +"t.dp.dly[9].a"->"t.dp.dly[9]._y"- +~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+ +"t.dp.dly[9]._y"->"t.dp.dly[9].y"- +~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+ +"t.dp.dly[10].a"->"t.dp.dly[10]._y"- +~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+ +"t.dp.dly[10]._y"->"t.dp.dly[10].y"- +~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+ +"t.dp.dly[11].a"->"t.dp.dly[11]._y"- +~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+ +"t.dp.dly[11]._y"->"t.dp.dly[11].y"- +~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+ +"t.dp.dly[12].a"->"t.dp.dly[12]._y"- +~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+ +"t.dp.dly[12]._y"->"t.dp.dly[12].y"- +~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+ +"t.dp.dly[13].a"->"t.dp.dly[13]._y"- +~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+ +"t.dp.dly[13]._y"->"t.dp.dly[13].y"- +~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+ +"t.dp.dly[14].a"->"t.dp.dly[14]._y"- +~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+ +"t.dp.dly[14]._y"->"t.dp.dly[14].y"- +~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+ += "t.dp.dly[6].y" "t.dp.mu2[3].b" += "t.dp.dly[6].a" "t.dp.dly[5].y" += "t.dp.dly[5].a" "t.dp.dly[4].y" += "t.dp.dly[4].a" "t.dp.and2[3].y" += "t.dp.dly[3].y" "t.dp.mu2[2].b" += "t.dp.dly[3].a" "t.dp.dly[2].y" += "t.dp.dly[2].a" "t.dp.and2[2].y" += "t.dp.dly[1].y" "t.dp.mu2[1].b" += "t.dp.dly[1].a" "t.dp.and2[1].y" += "t.dp.dly[0].y" "t.dp.mu2[0].b" += "t.dp.dly[0].a" "t.dp.and2[0].y" += "t.dp._a[1]" "t.dp.mu2[1].a" += "t.dp._a[1]" "t.dp.and2[1].a" += "t.dp._a[1]" "t.dp.mu2[0].y" += "t.dp._a[2]" "t.dp.mu2[2].a" += "t.dp._a[2]" "t.dp.and2[2].a" += "t.dp._a[2]" "t.dp.mu2[1].y" += "t.dp._a[3]" "t.dp.mu2[3].a" += "t.dp._a[3]" "t.dp.and2[3].a" += "t.dp._a[3]" "t.dp.mu2[2].y" += "t.dp.y" "t.dp.mu2[3].y" += "t.dp.y" "t.dp._a[4]" += "Vdd" "t.dp.supply.vdd" += "GND" "t.dp.supply.vss" += "t.s[0]" "t.dp.s[0]" += "t.s[1]" "t.dp.s[1]" += "t.s[2]" "t.dp.s[2]" += "t.s[3]" "t.dp.s[3]" diff --git a/test/unit_tests/delayprog_4/test.act b/test/unit_tests/delayprog_4/test.act new file mode 100644 index 0000000..ab4e929 --- /dev/null +++ b/test/unit_tests/delayprog_4/test.act @@ -0,0 +1,41 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/primitives.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc delayprog_4 (bool? s[4], a; bool! y){ + delayprog<4> dp(.a=a, .y=y, .s = s); + dp.supply.vss = GND; + dp.supply.vdd = Vdd; + +} + +delayprog_4 t; \ No newline at end of file diff --git a/test/unit_tests/delayprog_4/test.prsim b/test/unit_tests/delayprog_4/test.prsim new file mode 100644 index 0000000..02e71b6 --- /dev/null +++ b/test/unit_tests/delayprog_4/test.prsim @@ -0,0 +1,42 @@ +watchall + +system "echo '0'" + +set t.a 0 +set t.s[0] 1 +set t.s[1] 1 +set t.s[2] 1 +set t.s[3] 1 + +cycle +mode run + +assert t.y 0 + +system "echo '[] setting high'" +set t.a 1 +cycle +assert t.y 1 + +system "echo '[] setting low'" +set t.a 0 +cycle +assert t.y 0 + +system "echo '[] setting configs low'" +set t.s[0] 0 +set t.s[1] 0 +set t.s[2] 0 +set t.s[3] 0 +cycle +assert t.y 0 + +system "echo '[] setting high'" +set t.a 1 +cycle +assert t.y 1 + +system "echo '[] setting low'" +set t.a 0 +cycle +assert t.y 0 From 233c9a7d101a89cd750011c47d1cb40d9f6442ec Mon Sep 17 00:00:00 2001 From: alexmadison Date: Tue, 1 Mar 2022 15:27:27 +0100 Subject: [PATCH 2/3] cleaned up minor --- dataflow_neuro/primitives.act | 4 ---- 1 file changed, 4 deletions(-) diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 4dd5abe..e4d60a6 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -603,10 +603,6 @@ namespace tmpl { MUX2_X1 mu2[N]; DLY4_X1 dly[(1< Date: Tue, 1 Mar 2022 15:28:22 +0100 Subject: [PATCH 3/3] added DLY4 cell --- dataflow_neuro/cell_lib_std.act | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/dataflow_neuro/cell_lib_std.act b/dataflow_neuro/cell_lib_std.act index 2ef126d..370a32f 100644 --- a/dataflow_neuro/cell_lib_std.act +++ b/dataflow_neuro/cell_lib_std.act @@ -99,6 +99,18 @@ namespace tmpl { sizing { _y {-6,2}; y {-12,4} } } + /*-- delay cells --*/ + // TODO properly + + export defcell DLY4_X1(bool! y; bool? a, vdd, vss) + { + bool _y; + prs { + a => _y- + _y => y- + } + } + /*-- simple gates --*/