From 04d12338b76a481114715f1003460b8ae352642d Mon Sep 17 00:00:00 2001 From: Michele Date: Tue, 15 Mar 2022 08:16:59 +0100 Subject: [PATCH] continued register_rw --- dataflow_neuro/registers.act | 26 ++++++++++++++----------- test/unit_tests/register_wrw/test.prsim | 17 +++++++++++++++- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index 0b6dabe..d794ed3 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -55,9 +55,7 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of data[1< _in_temp; - (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];) - vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply); + vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply); sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply); // Generation of the fake clock pulse (inverted because the ff clocks are low_active) delayprog clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply); @@ -175,13 +173,16 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2 out; d1of d ) AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss); //Reset Buffers - bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl]; + bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl]; BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss); - sigbuf reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply); + sigbuf reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply); + sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply); + //Creating the encoder andtree atree[nw]; - AND2_X1 and_encoder[nw]; + OR2_X1 or_encoder[nw]; + INV_X1 inv_encoder[nw]; // Creating the different flip flop arrays bool _out_encoder[nw]; DFFQ_R_X1 ff[nw*wl]; @@ -201,11 +202,14 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2 out; d1of d ) // WRITE: Activating the fake clock for the right word atree[word_idx].out = _out_encoder[word_idx]; - and_encoder[word_idx].a = _out_encoder[word_idx]; - and_encoder[word_idx].b = _clock[word_idx]; - and_encoder[word_idx].y = _clock_word_temp[word_idx]; - and_encoder[word_idx].vdd = supply.vdd; - and_encoder[word_idx].vss = supply.vss; + inv_encoder[word_idx].a = _out_encoder[word_idx]; + inv_encoder[word_idx].y = or_encoder[word_idx].a; + inv_encoder[word_idx].vdd = supply.vdd; + inv_encoder[word_idx].vss = supply.vss; + or_encoder[word_idx].b = _clock[word_idx]; + or_encoder[word_idx].y = _clock_word_temp[word_idx]; + or_encoder[word_idx].vdd = supply.vdd; + or_encoder[word_idx].vss = supply.vss; clock_buffer[word_idx].in = _clock_word_temp[word_idx]; clock_buffer[word_idx].supply = supply; // READ: Selecting the right word to read if read is high diff --git a/test/unit_tests/register_wrw/test.prsim b/test/unit_tests/register_wrw/test.prsim index bb66528..d5ae286 100644 --- a/test/unit_tests/register_wrw/test.prsim +++ b/test/unit_tests/register_wrw/test.prsim @@ -3,6 +3,7 @@ system "echo '[0] start test'" system "echo '----------------------------------------------------------'" set-qdi-channel-neutral "t.in" 5 +set-qdi-channel-neutral "t.out" 4 set t.data[0].d[0] 0 set t.data[0].d[1] 0 set t.data[1].d[0] 0 @@ -11,9 +12,15 @@ set t.dly_cfg[0] 1 set t.dly_cfg[1] 1 set t.out.a 0 set t.out.v 0 +cycle #set t.registers._in_write.a 0 set Reset 0 +set t.dly_cfg[0] 1 +set t.dly_cfg[1] 1 cycle +assert-qdi-channel-neutral "t.in" 5 +assert-qdi-channel-neutral "t.out" 4 +# There shouldnt be any status X status X #mode run cycle @@ -45,21 +52,29 @@ assert t.registers.ff[0].q 1 assert t.registers.ff[1].q 1 assert t.registers.ff[2].q 0 assert t.registers.ff[3].q 0 +assert t.registers.ff[4].q 0 +assert t.registers.ff[5].q 0 +assert t.registers.ff[6].q 0 +assert t.registers.ff[7].q 0 system "echo '[3] first writing done'" system "echo '----------------------------------------------------------'" set-qdi-channel-valid "t.in" 5 16 -# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here) +# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here) cycle +assert t.registers._clock_temp_inv 1 assert-qdi-channel-valid "t.out" 4 3 set t.out.v 1 cycle set t.out.a 1 +assert t.registers._clock_temp_inv 1 cycle assert t.in.a 1 set-qdi-channel-neutral "t.in" 5 +assert t.registers._clock_temp_inv 1 cycle +assert t.registers._clock_temp_inv 1 assert t.registers.ff[0].q 1 assert t.registers.ff[1].q 1 assert t.registers.ff[2].q 0