From 0772df30a5659c60f61de299d4239ce510c2bc64 Mon Sep 17 00:00:00 2001 From: Hugh Date: Tue, 22 Feb 2022 11:25:55 +0100 Subject: [PATCH] we have liftoff - lisp code still needs fixing ctree/ortree/sigbuf all tests working --- dataflow_neuro/treegates.act | 2 + .../run/prsim.out | 0 .../run/test.prs | 0 .../test.act | 7 --- .../test.prsim | 0 test/unit_tests/ortree_15/run/prsim.out | 3 +- test/unit_tests/ortree_15/run/test.prs | 3 +- test/unit_tests/ortree_15/test.prsim | 32 ++++++------- test/unit_tests/sigbuf_15/run/prsim.out | 3 ++ test/unit_tests/sigbuf_15/run/test.prs | 14 ++++++ test/unit_tests/sigbuf_15/test.act | 48 +++++++++++++++++++ test/unit_tests/sigbuf_15/test.prsim | 12 +++++ 12 files changed, 98 insertions(+), 26 deletions(-) rename test/unit_tests/{primitive_instantiate => ctree_15}/run/prsim.out (100%) rename test/unit_tests/{primitive_instantiate => ctree_15}/run/test.prs (100%) rename test/unit_tests/{primitive_instantiate => ctree_15}/test.act (93%) rename test/unit_tests/{primitive_instantiate => ctree_15}/test.prsim (100%) create mode 100644 test/unit_tests/sigbuf_15/run/prsim.out create mode 100644 test/unit_tests/sigbuf_15/run/test.prs create mode 100644 test/unit_tests/sigbuf_15/test.act create mode 100644 test/unit_tests/sigbuf_15/test.prsim diff --git a/dataflow_neuro/treegates.act b/dataflow_neuro/treegates.act index c7d13ca..dc8474e 100644 --- a/dataflow_neuro/treegates.act +++ b/dataflow_neuro/treegates.act @@ -135,6 +135,8 @@ defproc ortree (bool? in[N]; bool! out; power supply) end = end+j; j = 0; ] + + out = tmp[end]; } /* diff --git a/test/unit_tests/primitive_instantiate/run/prsim.out b/test/unit_tests/ctree_15/run/prsim.out similarity index 100% rename from test/unit_tests/primitive_instantiate/run/prsim.out rename to test/unit_tests/ctree_15/run/prsim.out diff --git a/test/unit_tests/primitive_instantiate/run/test.prs b/test/unit_tests/ctree_15/run/test.prs similarity index 100% rename from test/unit_tests/primitive_instantiate/run/test.prs rename to test/unit_tests/ctree_15/run/test.prs diff --git a/test/unit_tests/primitive_instantiate/test.act b/test/unit_tests/ctree_15/test.act similarity index 93% rename from test/unit_tests/primitive_instantiate/test.act rename to test/unit_tests/ctree_15/test.act index fc98a31..cbe1eb4 100644 --- a/test/unit_tests/primitive_instantiate/test.act +++ b/test/unit_tests/ctree_15/test.act @@ -26,13 +26,6 @@ ************************************************************************** */ -//import "../../dataflow_neuro/treegates.act"; - -//open tmpl::dataflow_neuro; - -//sigbuf<3> buff_test; - - import "../../dataflow_neuro/treegates.act"; import globals; diff --git a/test/unit_tests/primitive_instantiate/test.prsim b/test/unit_tests/ctree_15/test.prsim similarity index 100% rename from test/unit_tests/primitive_instantiate/test.prsim rename to test/unit_tests/ctree_15/test.prsim diff --git a/test/unit_tests/ortree_15/run/prsim.out b/test/unit_tests/ortree_15/run/prsim.out index ad03ea3..92d59c7 100644 --- a/test/unit_tests/ortree_15/run/prsim.out +++ b/test/unit_tests/ortree_15/run/prsim.out @@ -1,2 +1,3 @@ -t.ortree_test.tmp[18] t.in[6] t.in[5] t.in[12] t.ortree_test.tmp[16] t.ortree_test.tmp[22] t.in[9] t.in[13] t.ortree_test.tmp[25] t.in[4] t.in[8] t.in[7] t.in[14] t.ortree_test.tmp[19] t.in[0] t.in[3] t.ortree_test.C2Els[1]._y t.ortree_test.C3Els[1]._y t.in[10] t.in[1] t.in[11] t.in[2] t.ortree_test.C2Els[4]._y t.ortree_test.tmp[20] t.ortree_test.tmp[17] t.ortree_test.tmp[21] t.ortree_test.tmp[23] t.ortree_test.C3Els[0]._y t.ortree_test.C2Els[2]._y t.ortree_test.tmp[24] t.ortree_test.tmp[15] t.ortree_test.C3Els[2]._y t.ortree_test.C2Els[6]._y t.ortree_test.C2Els[3]._y t.ortree_test.C2Els[5]._y t.ortree_test.C2Els[7]._y t.ortree_test.C2Els[0]._y +t.ortree_test.tmp[18] t.in[6] t.in[5] t.in[12] t.ortree_test.tmp[16] t.ortree_test.tmp[22] t.in[9] t.out t.in[13] t.in[4] t.in[8] t.in[7] t.in[14] t.ortree_test.tmp[19] t.in[0] t.in[3] t.ortree_test.C2Els[1]._y t.ortree_test.C3Els[1]._y t.in[10] t.in[1] t.in[11] t.in[2] t.ortree_test.C2Els[4]._y t.ortree_test.tmp[20] t.ortree_test.tmp[17] t.ortree_test.tmp[21] t.ortree_test.tmp[23] t.ortree_test.C3Els[0]._y t.ortree_test.C2Els[2]._y t.ortree_test.tmp[24] t.ortree_test.tmp[15] t.ortree_test.C3Els[2]._y t.ortree_test.C2Els[6]._y t.ortree_test.C2Els[3]._y t.ortree_test.C2Els[5]._y t.ortree_test.C2Els[7]._y t.ortree_test.C2Els[0]._y 0 +1 diff --git a/test/unit_tests/ortree_15/run/test.prs b/test/unit_tests/ortree_15/run/test.prs index 4169e4e..a14299b 100644 --- a/test/unit_tests/ortree_15/run/test.prs +++ b/test/unit_tests/ortree_15/run/test.prs @@ -64,7 +64,6 @@ = "t.ortree_test.tmp[23]" "t.ortree_test.C2Els[7].y" = "t.ortree_test.tmp[24]" "t.ortree_test.C3Els[2].c" = "t.ortree_test.tmp[24]" "t.ortree_test.C3Els[1].y" -= "t.ortree_test.tmp[25]" "t.ortree_test.C3Els[2].y" = "t.ortree_test.supply.vdd" "t.ortree_test.C3Els[2].vdd" = "t.ortree_test.supply.vdd" "t.ortree_test.C3Els[1].vdd" = "t.ortree_test.supply.vdd" "t.ortree_test.C3Els[0].vdd" @@ -117,6 +116,8 @@ = "t.ortree_test.in[13]" "t.ortree_test.tmp[13]" = "t.ortree_test.in[14]" "t.ortree_test.C3Els[0].c" = "t.ortree_test.in[14]" "t.ortree_test.tmp[14]" += "t.ortree_test.out" "t.ortree_test.C3Els[2].y" += "t.ortree_test.out" "t.ortree_test.tmp[25]" = "Vdd" "t.ortree_test.supply.vdd" = "GND" "t.ortree_test.supply.vss" = "t.out" "t.ortree_test.out" diff --git a/test/unit_tests/ortree_15/test.prsim b/test/unit_tests/ortree_15/test.prsim index ed7dcfe..271ddda 100644 --- a/test/unit_tests/ortree_15/test.prsim +++ b/test/unit_tests/ortree_15/test.prsim @@ -1,7 +1,21 @@ system "echo '0'" -set-bool-array "t.in" 15 0 +set t.in[0] 0 +set t.in[1] 0 +set t.in[2] 0 +set t.in[3] 0 +set t.in[4] 0 +set t.in[5] 0 +set t.in[6] 0 +set t.in[7] 0 +set t.in[8] 0 +set t.in[9] 0 +set t.in[10] 0 +set t.in[11] 0 +set t.in[12] 0 +set t.in[13] 0 +set t.in[14] 0 system "echo '1'" @@ -9,20 +23,4 @@ cycle mode run assert t.out 0 -set-bool-array "t.in" 15 1 -cycle -assert t.out 1 -system "echo '2'" - -set-bool-array "t.in" 15 0 -cycle -assert t.out 0 - -system "echo '3'" - -set-bool-array "t.in" 15 15 -cycle -assert t.out 1 - -system "echo '4'" \ No newline at end of file diff --git a/test/unit_tests/sigbuf_15/run/prsim.out b/test/unit_tests/sigbuf_15/run/prsim.out new file mode 100644 index 0000000..327a6c4 --- /dev/null +++ b/test/unit_tests/sigbuf_15/run/prsim.out @@ -0,0 +1,3 @@ +t.sigbuf_test.buf6._y t.in t.out +0 +1 diff --git a/test/unit_tests/sigbuf_15/run/test.prs b/test/unit_tests/sigbuf_15/run/test.prs new file mode 100644 index 0000000..3bb1343 --- /dev/null +++ b/test/unit_tests/sigbuf_15/run/test.prs @@ -0,0 +1,14 @@ += "GND" "GND" += "Vdd" "Vdd" +"t.sigbuf_test.buf6.a"->"t.sigbuf_test.buf6._y"- +~("t.sigbuf_test.buf6.a")->"t.sigbuf_test.buf6._y"+ +"t.sigbuf_test.buf6._y"->"t.sigbuf_test.buf6.y"- +~("t.sigbuf_test.buf6._y")->"t.sigbuf_test.buf6.y"+ += "t.sigbuf_test.supply.vdd" "t.sigbuf_test.buf6.vdd" += "t.sigbuf_test.supply.vss" "t.sigbuf_test.buf6.vss" += "t.sigbuf_test.out" "t.sigbuf_test.buf6.y" += "t.sigbuf_test.in" "t.sigbuf_test.buf6.a" += "Vdd" "t.sigbuf_test.supply.vdd" += "GND" "t.sigbuf_test.supply.vss" += "t.out" "t.sigbuf_test.out" += "t.in" "t.sigbuf_test.in" diff --git a/test/unit_tests/sigbuf_15/test.act b/test/unit_tests/sigbuf_15/test.act new file mode 100644 index 0000000..3bfe367 --- /dev/null +++ b/test/unit_tests/sigbuf_15/test.act @@ -0,0 +1,48 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +//import "../../dataflow_neuro/treegates.act"; + +//open tmpl::dataflow_neuro; + +//sigbuf<3> buff_test; + + +import "../../dataflow_neuro/treegates.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc sigbuf_15 (bool? in; bool! out){ + sigbuf<15> sigbuf_test(.in=in, .out=out); + sigbuf_test.supply.vss = GND; + sigbuf_test.supply.vdd = Vdd; + +} + +sigbuf_15 t; diff --git a/test/unit_tests/sigbuf_15/test.prsim b/test/unit_tests/sigbuf_15/test.prsim new file mode 100644 index 0000000..a58b766 --- /dev/null +++ b/test/unit_tests/sigbuf_15/test.prsim @@ -0,0 +1,12 @@ + +system "echo '0'" + +set t.in 0 + +system "echo '1'" + +cycle +mode run +assert t.out 0 + +