From 0a5a2714092a3d970b5d296f633eb14a44a07a4e Mon Sep 17 00:00:00 2001 From: Hugh Date: Mon, 21 Feb 2022 17:59:41 +0100 Subject: [PATCH] Trying to get ortree test working --- dataflow_neuro/treegates.act | 25 +++++++++++------ test/unit_tests/helper.scm | 23 +++++++++++++++ test/unit_tests/init.prs | 2 ++ test/unit_tests/init_qdi.prsim | 2 ++ test/unit_tests/ortree_15/run/test.prs | 2 ++ test/unit_tests/ortree_15/test.act | 39 ++++++++++++++++++++++++++ test/unit_tests/ortree_15/test.prsim | 19 +++++++++++++ 7 files changed, 103 insertions(+), 9 deletions(-) create mode 100644 test/unit_tests/ortree_15/run/test.prs create mode 100644 test/unit_tests/ortree_15/test.act create mode 100644 test/unit_tests/ortree_15/test.prsim diff --git a/dataflow_neuro/treegates.act b/dataflow_neuro/treegates.act index 0d9ce1d..17f723e 100644 --- a/dataflow_neuro/treegates.act +++ b/dataflow_neuro/treegates.act @@ -37,16 +37,14 @@ export deftype power (bool?! vdd, vss) { } -export template -defproc ortree (bool? in[N]; bool out) +export template +defproc ortree (bool? in[N]; bool! out; power supply) { bool tout; { N > 0 : "What?" }; pint i, end, j; - pbool isinv; - isinv = invert; i = 0; end = N-1; @@ -81,6 +79,12 @@ defproc ortree (bool? in[N]; bool out) OR2_X1 C2Els[lenTree2Count]; OR3_X1 C3Els[lenTree3Count]; + (h:lenTree2Count:C2Els[h].vdd = supply.vdd;) + (h:lenTree3Count:C3Els[h].vdd = supply.vdd;) + + (h:lenTree2Count:C2Els[h].vss = supply.vss;) + (h:lenTree3Count:C3Els[h].vss = supply.vss;) + /* Reset the variables we just stole lol */ i = 0; end = N-1; @@ -137,16 +141,14 @@ defproc ortree (bool? in[N]; bool out) * Build a completion tree using a combination of 2-input and 3-input * C-elements */ -export template -defproc ctree (bool? in[N]; bool out) +export template +defproc ctree (bool? in[N]; bool! out; power supply) { bool tout; { N > 0 : "What?" }; pint i, end, j; - pbool isinv; - isinv = invert; i = 0; end = N-1; @@ -170,7 +172,6 @@ defproc ctree (bool? in[N]; bool out) /*-- update range that has to be combined --*/ i = end+1; end = end+j; - j = 0; ] /* array that holds ALL the nodes in the completion tree */ @@ -181,6 +182,12 @@ defproc ctree (bool? in[N]; bool out) A_2C_B_X1 C2Els[lenTree2Count]; A_3C_B_X1 C3Els[lenTree3Count]; + (h:lenTree2Count:C2Els[h].vdd = supply.vdd;) + (h:lenTree3Count:C3Els[h].vdd = supply.vdd;) + + (h:lenTree2Count:C2Els[h].vss = supply.vss;) + (h:lenTree3Count:C3Els[h].vss = supply.vss;) + /* Reset the variables we just stole lol */ i = 0; end = N-1; diff --git a/test/unit_tests/helper.scm b/test/unit_tests/helper.scm index 82473f2..d35fe23 100644 --- a/test/unit_tests/helper.scm +++ b/test/unit_tests/helper.scm @@ -122,3 +122,26 @@ (define assert-var-bool (lambda (x v) (assert-var-int x 1 v))) + +(define set-bool-array + (lambda (ch width val) + (letrec ((ch) + (helper + (lambda (i v) + (cond + ((=? i width) #t) + (#t (let ((tmp (string-append ch (string-append "[" (string-append (number->string i) "]"))))) + (begin + (set tmp (% v 2)) + (helper (+ 1 i) (truncate (/ v 2))) + ) + )) + ) + ) + )) + (begin + (helper 0 val) + ) + ) + ) +) diff --git a/test/unit_tests/init.prs b/test/unit_tests/init.prs index e69de29..0ff1a11 100644 --- a/test/unit_tests/init.prs +++ b/test/unit_tests/init.prs @@ -0,0 +1,2 @@ += "GND" "GND" += "Vdd" "Vdd" \ No newline at end of file diff --git a/test/unit_tests/init_qdi.prsim b/test/unit_tests/init_qdi.prsim index b9af213..91fe00e 100644 --- a/test/unit_tests/init_qdi.prsim +++ b/test/unit_tests/init_qdi.prsim @@ -1,6 +1,8 @@ initialize load-scm "helper.scm" random +set GND 0 +set Vdd 1 mode reset cycle diff --git a/test/unit_tests/ortree_15/run/test.prs b/test/unit_tests/ortree_15/run/test.prs new file mode 100644 index 0000000..0ff1a11 --- /dev/null +++ b/test/unit_tests/ortree_15/run/test.prs @@ -0,0 +1,2 @@ += "GND" "GND" += "Vdd" "Vdd" \ No newline at end of file diff --git a/test/unit_tests/ortree_15/test.act b/test/unit_tests/ortree_15/test.act new file mode 100644 index 0000000..0d6a4d8 --- /dev/null +++ b/test/unit_tests/ortree_15/test.act @@ -0,0 +1,39 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/treegates.act"; + +open tmpl::dataflow_neuro; + +defproc ortree_15 (bool? in[15]; bool! out){ + ortree<15> ortree_test(.in=in, .out=out); + ortree_test.supply.vss = GND; + ortree_test.supply.vdd = Vdd; + +} + diff --git a/test/unit_tests/ortree_15/test.prsim b/test/unit_tests/ortree_15/test.prsim new file mode 100644 index 0000000..1e3f700 --- /dev/null +++ b/test/unit_tests/ortree_15/test.prsim @@ -0,0 +1,19 @@ +set-bool-array "t.in" 15 0 +cycle +mode run +assert t.out 0 + +set-bool-array "t.in" 15 1 +cycle +assert t.out 1 + +set-bool-array "t.in" 15 0 +cycle +assert t.out 0 + + +set-bool-array "t.in" 15 15 +cycle +assert t.out 1 + +