From 1586adc0e1e3dfc5b455e8b6ed36aa271f55dd0b Mon Sep 17 00:00:00 2001 From: alexmadison Date: Mon, 9 May 2022 18:04:17 +0200 Subject: [PATCH] started adding mapper --- dataflow_neuro/chips.act | 203 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act index 50c43a3..4022b16 100644 --- a/dataflow_neuro/chips.act +++ b/dataflow_neuro/chips.act @@ -540,6 +540,209 @@ defproc texel_dualcore (bd in, out; } + + + + + +export template +defproc texel_dualcore_mapper (bd in, out; + + Mx1of2 c1_reg_data[REG_M]; + + bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y]; + bool? c1_dec_ackB[N_SYN_X]; + a1of1 c1_syn_pu[N_SYN_X]; + + a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y]; + a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y]; + + bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y]; + bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y]; + bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN]; + bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN]; + bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN]; + + bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X], + c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X]; + + Mx1of2 c2_reg_data[REG_M]; + + bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y]; + bool? c2_dec_ackB[N_SYN_X]; + a1of1 c2_syn_pu[N_SYN_X]; + + a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y]; + a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y]; + + bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y]; + bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y]; + bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN]; + bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN]; + bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN]; + + bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X], + c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X]; + + bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2]; + bool? loopback_en; + power supply; + bool? reset_B, reset_reg_B, reset_syn_stge_BI; + + // MAPPER STUFF + + avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr) + avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr) + avMx1of2<15> in_sram_r; // Readout packets from SRAM (data only) + avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr) + + ){ + + // Reset buffers + bool _reset_BX; + BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss); + + bd2qdi _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2, + .reset_B = _reset_BX, .supply = supply); + fifo fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply); + + fork _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply); + + // Loopback + fifo fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply); + dropper_static _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en, + .supply = supply); + fifo fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply); + + + + // dmx to SRAM + bool to_sram, to_cores; + demux<32> sram_dmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX); + sram_dmx.cond.d.d[0].t = to_sram; + sram_dmx.cond.d.d[0].f = to_cores; + AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t, + .y = to_sram, + .vdd = supply.vdd, .vss = supply.vss); + OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f, + .y = to_cores, + .vdd = supply.vdd, .vss = supply.vss); + slice_data<32, 0, 29> pre_sram_slice(.in = sram_dmx.out2, .supply = supply); + out_sram_wr.a = pre_sram_slice.out.a; + out_sram_wr.v = pre_sram_slice.out.v; + (i:29:out_sram_wr.d.d[i] = pre_sram_slice.out.d.d[i];) + out_sram_wr.d.d[29] = pre_sram_slice.in.d.d[31]; + + + // Onwards to core demux + fifo fifo_fork2dmx(.in = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply); + demux_bit_msb core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply); + fifo fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply); + fifo fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply); + + // Cores + texel_core + core1(.in = fifo_dmx2core1.out, + + .reg_data = c1_reg_data, + // .synapses = c1_synapses, + // .neurons = c1_neurons, + + .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y, + .dec_ackB = c1_dec_ackB, + .syn_pu = c1_syn_pu, + + .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny, + .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y, + + .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y, + .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y, + .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI, + .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO, + .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO, + + .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI, + .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO, + .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO, + + .supply = supply + ); + + + texel_core + core2(.in = fifo_dmx2core2.out, + + .reg_data = c2_reg_data, + // .synapses = c2_synapses, + // .neurons = c2_neurons, + + .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y, + .dec_ackB = c2_dec_ackB, + .syn_pu = c2_syn_pu, + + .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny, + .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y, + + .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y, + .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y, + .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI, + .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO, + .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO, + + .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI, + .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO, + .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO, + + .supply = supply + ); + + fifo fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply); + fifo fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply); + + + // Merge cores + append append_core1(.in = fifo_core1out.out, .supply = supply); + append append_core2(.in = fifo_core2out.out, .supply = supply); + merge merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out, + .supply = supply, .reset_B = _reset_BX); + + // Merge cores and loopback + merge merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out, + .reset_B = _reset_BX, .supply = supply); + + // qdi2bd + fifo fifo_mrg2bd(.in = merge_drop8core.out, + .reset_B = _reset_BX, .supply = supply); + qdi2bd _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg, + .reset_B = _reset_BX, .supply = supply); + +} + + + + + + + + + + + + + + + + } }