From 17cbc269a6057fbf823a860d9d3f8e2418792695 Mon Sep 17 00:00:00 2001
From: alexmadison <git@mdsn.co.uk>
Date: Wed, 13 Apr 2022 18:44:41 +0200
Subject: [PATCH] altered dly cfg to use not(t) rather than f

---
 dataflow_neuro/chips.act | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act
index 54d7d6f..78ca6a4 100644
--- a/dataflow_neuro/chips.act
+++ b/dataflow_neuro/chips.act
@@ -96,7 +96,13 @@ defproc texel_core (avMx1of2<N_IN> in, out;
         .out = synapses,
         .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
         .supply = supply, .reset_B = _reset_BX);
-    (i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    ) // This sexy hack means that the inverters are max delay throughout the register flush operations.
 
     // Neurons + encoder
     pint NC_NRN;