From 1b7e39bc00899741653b923d0db874d4fd36bffb Mon Sep 17 00:00:00 2001 From: alexmadison Date: Wed, 2 Mar 2022 09:48:41 +0100 Subject: [PATCH] coders.act file init --- dataflow_neuro/coders.act | 161 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 dataflow_neuro/coders.act diff --git a/dataflow_neuro/coders.act b/dataflow_neuro/coders.act new file mode 100644 index 0000000..b5f6ffd --- /dev/null +++ b/dataflow_neuro/coders.act @@ -0,0 +1,161 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ +import "../../dataflow_neuro/cell_lib_async.act"; +import "../../dataflow_neuro/cell_lib_std.act"; +import "../../dataflow_neuro/treegates.act"; +import "../../dataflow_neuro/primitives.act"; +// import tmpl::dataflow_neuro; +// import tmpl::dataflow_neuro; +import std::channel; +open std::channel; + +namespace tmpl { + namespace dataflow_neuro { + + + + /** + * 2D decoder which uses a configurable delay from the VCtrees to buffer ack. + * Nx is the x size of the decoder array + * NxC is the number of wires in the x channel. + * Thus NxC should be something like NxC = ceil(log2(Nx)) + * but my guess is that we can't do logs... + * N_dly_cfg is the number of config bits in the ACK delay line, + * with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells. + */ + // export template + // defproc decoder_2d_dly (avMx1of2 in; bool? dly_cfg[N_dly_cfg], reset_B; power supply) { + + // // Buffer to recieve concat(x,y) address packet + // buffer addr_buf(.in = in, .reset_B = reset_B, .supply = supply); + // // NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON + + // // Validity trees + // vtree vtree_x (.power = supply); + // vtree vtree_y (.power = supply); + // (i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;) + // (i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;) + // (i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;) + // (i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;) + + // // Delay ack line. Ack line is delayed (but not the val) + // A_2X_B_X1 C2el(.a = vtree_x.out, .b = vtree_y.out, .supply = supply); + // addr_buf.out.v = C2el.y; + // delayprog dly(.in = C2el.y, .s = dly_cfg, .supply = supply); + // delayprog.out = addr_buf.out.a; + + // // AND trees + + // pint bitval; + + // andtree atree_x[Nx]; + // (i:0..Nx-1: + // (j:0..NxC: + // bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j + // [bitval == 1 -> + // atree_x[i].in[j] = addr_buf.out.d.d[j].t + // []bitval == 0 -> + // atree_x[i].in[j] = addr_buf.out.d.d[j].f + // ] + // ) + // ) + + // andtree atree_y[Ny]; + // (i:0..Ny-1: + // (j:0..NyC: + // bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j + // [bitval == 1 -> + // atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t + // []bitval == 0 -> + // atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f + // ] + // ) + // ) + + + + // // Connect stuff to vdd/vss + // (i:0..Nx-1:atree_x[i].supply = supply) + + + + + + + + + + // //control + // bool _en, _reset_BX,_reset_BXX[N]; + // A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + // A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + + + // BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + // sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); + + // //validity + // bool _in_v; + // vtree vc(.in=in.d,.out=_in_v,.supply=supply); + // BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); + + // //function + // bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N]; + // A_2C1N_RB_X4 f_buf_func[N]; + // A_2C1N_RB_X4 t_buf_func[N]; + // sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); + // sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); + // INV_X1 out_a_inv(.a=out.a,.y=_out_a_B); + // sigbuf out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t); + // sigbuf out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f); + // // check if you can also do single var to array connect a=b[N] + // // and remove them from the loop + // (i:N: + // f_buf_func[i].y=out.d.d[i].f; + // t_buf_func[i].y=out.d.d[i].t; + // f_buf_func[i].c1=_en_X_f[i]; + // t_buf_func[i].c1=_en_X_t[i]; + // f_buf_func[i].c2=_out_a_BX_f[i]; + // t_buf_func[i].c2=_out_a_BX_t[i]; + // f_buf_func[i].n1=in.d.d[i].f; + // t_buf_func[i].n1=in.d.d[i].t; + // f_buf_func[i].vdd=supply.vdd; + // t_buf_func[i].vdd=supply.vdd; + // f_buf_func[i].vss=supply.vss; + // t_buf_func[i].vss=supply.vss; + // t_buf_func[i].pr_B = _reset_BXX[i]; + // t_buf_func[i].sr_B = _reset_BXX[i]; + // f_buf_func[i].pr_B = _reset_BXX[i]; + // f_buf_func[i].sr_B = _reset_BXX[i]; + ) + } + + + } + +} \ No newline at end of file