diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 40f8ba5..2129d83 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -150,92 +150,92 @@ namespace tmpl { ) } - export template - defproc demux (avMx1of2 in; avMx1of2 out1; avMx1of2 out2; bool? reset_B, c_t, c_f; power supply) { - //control - bool _en, _reset_BX,_reset_BXX[N], _out_v; + // export template + // defproc demux (avMx1of2 in; avMx1of2 out1; avMx1of2 out2; bool? reset_B, c_t, c_f; power supply) { + // //control + // bool _en, _reset_BX,_reset_BXX[N], _out_v; - OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss); - A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); - A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); - BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); - sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); - A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + // OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss); + // A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); + // A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + // BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + // sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); + // A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); - //validity - bool _in_v, _c_f_buf, _c_t_buf, _c_v, _in_c_v_; + // //validity + // bool _in_v, _c_f_buf, _c_t_buf, _c_v, _in_c_v_; - sigbuf c_buf_t(.in=c_t, .out=_c_t_buf); - sigbuf c_buf_f(.in=c_f, .out=_c_f_buf); + // sigbuf c_buf_t(.in=c_t, .out=_c_t_buf); + // sigbuf c_buf_f(.in=c_f, .out=_c_f_buf); - OR2_X1 c_f_c_t_or(.a=c_t, .b=c_f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss); - ctree vc(.in=in.d,.out=_in_v,.supply=supply); + // OR2_X1 c_f_c_t_or(.a=c_t, .b=c_f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss); + // ctree vc(.in=in.d,.out=_in_v,.supply=supply); - A_2C_RB_X4 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss); - BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); + // A_2C_RB_X4 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss); + // BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); - //function - //func buffer out1 - bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N]; - A_2C2N_RB_X4 out1_f_buf_func[N]; - A_2C2N_RB_X4 out1_t_buf_func[N]; - sigbuf out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply); - sigbuf out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply); - INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B); - sigbuf out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t); - sigbuf out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f); - (i:N: - out1_f_buf_func[i].y=out1.d.d[i].f; - out1_t_buf_func[i].y=out1.d.d[i].t; - out1_f_buf_func[i].c1=_en1_X_f[i]; - out1_t_buf_func[i].c1=_en1_X_t[i]; - out1_f_buf_func[i].c2=_out1_a_BX_f[i]; - out1_t_buf_func[i].c2=_out1_a_BX_t[i]; - out1_f_buf_func[i].n1=in.d.d[i].f; - out1_t_buf_func[i].n1=in.d.d[i].t; - out1_f_buf_func[i].vdd=supply.vdd; - out1_t_buf_func[i].vdd=supply.vdd; - out1_f_buf_func[i].vss=supply.vss; - out1_t_buf_func[i].vss=supply.vss; - out1_t_buf_func[i].pr_B = _reset_BXX[i]; - out1_t_buf_func[i].sr_B = _reset_BXX[i]; - out1_f_buf_func[i].pr_B = _reset_BXX[i]; - out1_f_buf_func[i].sr_B = _reset_BXX[i]; - out1_f_buf_func[i].n2=_c_t_buf; - out1_t_buf_func[i].n2=_c_t_buf; - ) - //func buffer out2 - bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N]; - A_2C2N_RB_X4 out2_f_buf_func[N]; - A_2C2N_RB_X4 out2_t_buf_func[N]; - sigbuf out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply); - sigbuf out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply); - INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B); - sigbuf out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t); - sigbuf out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f); - (i:N: - out2_f_buf_func[i].y=out2.d.d[i].f; - out2_t_buf_func[i].y=out2.d.d[i].t; - out2_f_buf_func[i].c1=_en2_X_f[i]; - out2_t_buf_func[i].c1=_en2_X_t[i]; - out2_f_buf_func[i].c2=_out2_a_BX_f[i]; - out2_t_buf_func[i].c2=_out2_a_BX_t[i]; - out2_f_buf_func[i].n1=in.d.d[i].f; - out2_t_buf_func[i].n1=in.d.d[i].t; - out2_f_buf_func[i].vdd=supply.vdd; - out2_t_buf_func[i].vdd=supply.vdd; - out2_f_buf_func[i].vss=supply.vss; - out2_t_buf_func[i].vss=supply.vss; - out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1]; - out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1]; - out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1]; - out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1]; - out2_f_buf_func[i].n2=_c_f_buf; - out2_t_buf_func[i].n2=_c_f_buf; - ) + // //function + // //func buffer out1 + // bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N]; + // A_2C2N_RB_X4 out1_f_buf_func[N]; + // A_2C2N_RB_X4 out1_t_buf_func[N]; + // sigbuf out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply); + // sigbuf out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply); + // INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B); + // sigbuf out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t); + // sigbuf out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f); + // (i:N: + // out1_f_buf_func[i].y=out1.d.d[i].f; + // out1_t_buf_func[i].y=out1.d.d[i].t; + // out1_f_buf_func[i].c1=_en1_X_f[i]; + // out1_t_buf_func[i].c1=_en1_X_t[i]; + // out1_f_buf_func[i].c2=_out1_a_BX_f[i]; + // out1_t_buf_func[i].c2=_out1_a_BX_t[i]; + // out1_f_buf_func[i].n1=in.d.d[i].f; + // out1_t_buf_func[i].n1=in.d.d[i].t; + // out1_f_buf_func[i].vdd=supply.vdd; + // out1_t_buf_func[i].vdd=supply.vdd; + // out1_f_buf_func[i].vss=supply.vss; + // out1_t_buf_func[i].vss=supply.vss; + // out1_t_buf_func[i].pr_B = _reset_BXX[i]; + // out1_t_buf_func[i].sr_B = _reset_BXX[i]; + // out1_f_buf_func[i].pr_B = _reset_BXX[i]; + // out1_f_buf_func[i].sr_B = _reset_BXX[i]; + // out1_f_buf_func[i].n2=_c_t_buf; + // out1_t_buf_func[i].n2=_c_t_buf; + // ) + // //func buffer out2 + // bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N]; + // A_2C2N_RB_X4 out2_f_buf_func[N]; + // A_2C2N_RB_X4 out2_t_buf_func[N]; + // sigbuf out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply); + // sigbuf out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply); + // INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B); + // sigbuf out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t); + // sigbuf out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f); + // (i:N: + // out2_f_buf_func[i].y=out2.d.d[i].f; + // out2_t_buf_func[i].y=out2.d.d[i].t; + // out2_f_buf_func[i].c1=_en2_X_f[i]; + // out2_t_buf_func[i].c1=_en2_X_t[i]; + // out2_f_buf_func[i].c2=_out2_a_BX_f[i]; + // out2_t_buf_func[i].c2=_out2_a_BX_t[i]; + // out2_f_buf_func[i].n1=in.d.d[i].f; + // out2_t_buf_func[i].n1=in.d.d[i].t; + // out2_f_buf_func[i].vdd=supply.vdd; + // out2_t_buf_func[i].vdd=supply.vdd; + // out2_f_buf_func[i].vss=supply.vss; + // out2_t_buf_func[i].vss=supply.vss; + // out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1]; + // out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1]; + // out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1]; + // out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1]; + // out2_f_buf_func[i].n2=_c_f_buf; + // out2_t_buf_func[i].n2=_c_f_buf; + // ) - } + // } export template @@ -327,17 +327,27 @@ namespace tmpl { // sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); // //validity - - // //function + // bool _in1_v,_in2_v; + // a1of1 _in1_temp,_in2_temp,_out_temp; + // ctree vc1(.in=in1.d,.out=in1.v,.supply=supply); + // ctree vc2(.in=in2.d,.out=in2.v,.supply=supply); + // arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp) + // _in1_temp.r = in1.v + // _in2_temp.r = in2.v + // _in1_temp.a = + // _in1_temp.a = + // _out_temp.r = _out_temp.a + //function // } + export + defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply) + { + bool _y1_arb,_y2_arb; - // defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply) - // { - // bool _y1_arb,_y2_arb; - - // A_2C_B_X1 cel1(.c1 = out.a,.c2 = _y1_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss); - // A_2C_B_X1 cel2(.c1 = out.a,.c2 = _y2_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss); - // OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss); - // ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss); - // } + A_2C_B_X1 ack_cel1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss); + A_2C_B_X1 ack_cel2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss); + OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss); + ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss); + + } }} diff --git a/test/unit_tests/arbiter_handshake/run/prsim.out b/test/unit_tests/arbiter_handshake/run/prsim.out new file mode 100644 index 0000000..dc70d3b --- /dev/null +++ b/test/unit_tests/arbiter_handshake/run/prsim.out @@ -0,0 +1,63 @@ +t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.in1.a t.a.arbiter._y2 t.out.a t.a._y2_arb t.a._y1_arb t.a.ack_cel2._y t.in2.a t.a.or_cell._y t.a.ack_cel1._y + 0 t.in1.r : 0 + 0 t.out.a : 0 + 0 t.in2.r : 0 + 1 t.a.arbiter._y1 : 1 [by t.in1.r:=0] + 7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0] +t.out.r t.in1.a t.a._y2_arb t.a._y1_arb t.a.ack_cel2._y t.in2.a t.a.or_cell._y t.a.ack_cel1._y +[0] reset done + 7092 t.in1.r : 1 + 17559 t.a.arbiter._y1 : 0 [by t.in1.r:=1] + 17561 t.a._y1_arb : 1 [by t.a.arbiter._y1:=0] + 22314 t.a.or_cell._y : 0 [by t.a._y1_arb:=1] + 23451 t.out.r : 1 [by t.a.or_cell._y:=0] + 23451 t.out.a : 1 + 23565 t.a.ack_cel1._y : 0 [by t.out.a:=1] + 88931 t.in1.a : 1 [by t.a.ack_cel1._y:=0] + 90657 t.a._y2_arb : 0 [by t.in1.a:=1] +[1] test in1 done + 90657 t.in1.r : 0 + 90657 t.out.a : 0 + 90672 t.a.ack_cel2._y : 1 [by t.out.a:=0] +WARNING: weak-interference `t.a._y1_arb' +>> cause: t.a.arbiter._y1 (val: 1) +>> time: 90696 + 90696 t.a.arbiter._y1 : 1 [by t.in1.r:=0] +WARNING: weak-interference `t.a.or_cell._y' +>> cause: t.a._y1_arb (val: X) +>> time: 90709 + 90709 t.a._y1_arb : X [by t.a.arbiter._y1:=1] +WARNING: weak-interference `t.in1.a' +>> cause: t.a.ack_cel1._y (val: X) +>> time: 90749 + 90749 t.a.ack_cel1._y : X [by t.a._y1_arb:=X] +WARNING: weak-interference `t.a._y2_arb' +>> cause: t.in1.a (val: X) +>> time: 90769 + 90769 t.in1.a : X [by t.a.ack_cel1._y:=X] +WARNING: weak-interference `t.out.r' +>> cause: t.a.or_cell._y (val: X) +>> time: 91124 + 91124 t.a.or_cell._y : X [by t.a._y1_arb:=X] + 91163 t.in2.a : 0 [by t.a.ack_cel2._y:=1] + 91171 t.out.r : X [by t.a.or_cell._y:=X] + 91179 t.a._y1_arb : 1 [by t.in2.a:=0] + 96830 t.a._y2_arb : X [by t.in1.a:=X] + 135277 t.a.or_cell._y : 0 [by t.a._y1_arb:=1] + 149001 t.out.r : 1 [by t.a.or_cell._y:=0] +t.in1.a t.a._y2_arb t.a.ack_cel1._y +WRONG ASSERT: "t.out.r" has value 1 and not 0. +WRONG ASSERT: "t.in1.a" has value X and not 0. +[2] reset done + 149001 t.in2.r : 1 + 149005 t.a.arbiter._y2 : 0 [by t.in2.r:=1] + 158134 t.a._y2_arb : 1 [by t.a.arbiter._y2:=0] + 158134 t.out.a : 1 + 158149 t.a.ack_cel2._y : 0 [by t.out.a:=1] + 195080 t.in2.a : 1 [by t.a.ack_cel2._y:=0] +WARNING: unstable `t.a.ack_cel1._y'- +>> cause: t.a._y1_arb (val: 0) +>> time: 195135 + 195135 t.a._y1_arb : 0 [by t.in2.a:=1] + 201382 t.a.ack_cel1._y : X [by t.a._y1_arb:=0] +[3] test in2 done diff --git a/test/unit_tests/arbiter_handshake/run/prsim.pdf b/test/unit_tests/arbiter_handshake/run/prsim.pdf new file mode 100644 index 0000000..a15619a Binary files /dev/null and b/test/unit_tests/arbiter_handshake/run/prsim.pdf differ diff --git a/test/unit_tests/arbiter_handshake/run/test.prs b/test/unit_tests/arbiter_handshake/run/test.prs index 02d06ef..dfef2fb 100644 --- a/test/unit_tests/arbiter_handshake/run/test.prs +++ b/test/unit_tests/arbiter_handshake/run/test.prs @@ -1,3 +1,70 @@ = "GND" "GND" = "Vdd" "Vdd" = "Reset" "Reset" += "t.a.in1.d.d[0]" "t.a.in1.r" += "t.a.in1.a" "t.a.arbiter.d" += "t.a.in1.a" "t.a.ack_cel1.y" += "t.a.in1.d.d[0]" "t.a.arbiter.a" += "t.a.in1.d.d[0]" "t.a.in1.r" +~"t.a.ack_cel1.c1"&~"t.a.ack_cel1.c2"->"t.a.ack_cel1._y"+ +"t.a.ack_cel1.c1"&"t.a.ack_cel1.c2"->"t.a.ack_cel1._y"- +"t.a.ack_cel1._y"->"t.a.ack_cel1.y"- +~("t.a.ack_cel1._y")->"t.a.ack_cel1.y"+ +~"t.a.ack_cel2.c1"&~"t.a.ack_cel2.c2"->"t.a.ack_cel2._y"+ +"t.a.ack_cel2.c1"&"t.a.ack_cel2.c2"->"t.a.ack_cel2._y"- +"t.a.ack_cel2._y"->"t.a.ack_cel2.y"- +~("t.a.ack_cel2._y")->"t.a.ack_cel2.y"+ += "t.a.in2.d.d[0]" "t.a.in2.r" += "t.a.in2.a" "t.a.arbiter.c" += "t.a.in2.a" "t.a.ack_cel2.y" += "t.a.in2.d.d[0]" "t.a.arbiter.b" += "t.a.in2.d.d[0]" "t.a.in2.r" += "t.a.supply.vdd" "t.a.arbiter.vdd" += "t.a.supply.vdd" "t.a.or_cell.vdd" += "t.a.supply.vdd" "t.a.ack_cel2.vdd" += "t.a.supply.vdd" "t.a.ack_cel1.vdd" += "t.a.supply.vss" "t.a.arbiter.vss" += "t.a.supply.vss" "t.a.or_cell.vss" += "t.a.supply.vss" "t.a.ack_cel2.vss" += "t.a.supply.vss" "t.a.ack_cel1.vss" +"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"- +~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+ +"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"- +~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+ +~"t.a.arbiter._y1"|~"t.a.arbiter.c"->"t.a.arbiter.y1"+ +~(~"t.a.arbiter._y1"|~"t.a.arbiter.c")->"t.a.arbiter.y1"- +~"t.a.arbiter._y2"|~"t.a.arbiter.d"->"t.a.arbiter.y2"+ +~(~"t.a.arbiter._y2"|~"t.a.arbiter.d")->"t.a.arbiter.y2"- +mk_excllo("t.a.arbiter._y1","t.a.arbiter._y2") += "t.a._y1_arb" "t.a.arbiter.y1" += "t.a._y1_arb" "t.a.or_cell.a" += "t.a._y1_arb" "t.a.ack_cel1.c2" +"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"- +~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+ +"t.a.or_cell._y"->"t.a.or_cell.y"- +~("t.a.or_cell._y")->"t.a.or_cell.y"+ += "t.a.out.d.d[0]" "t.a.out.r" += "t.a.out.a" "t.a.ack_cel2.c1" += "t.a.out.a" "t.a.ack_cel1.c1" += "t.a.out.d.d[0]" "t.a.or_cell.y" += "t.a.out.d.d[0]" "t.a.out.r" += "t.a._y2_arb" "t.a.arbiter.y2" += "t.a._y2_arb" "t.a.or_cell.b" += "t.a._y2_arb" "t.a.ack_cel2.c2" += "Vdd" "t.a.supply.vdd" += "GND" "t.a.supply.vss" += "t.in1.d.d[0]" "t.in1.r" += "t.in1.r" "t.a.in1.r" += "t.in1.a" "t.a.in1.a" += "t.in1.d.d[0]" "t.a.in1.d.d[0]" += "t.in1.d.d[0]" "t.in1.r" += "t.out.d.d[0]" "t.out.r" += "t.out.r" "t.a.out.r" += "t.out.a" "t.a.out.a" += "t.out.d.d[0]" "t.a.out.d.d[0]" += "t.out.d.d[0]" "t.out.r" += "t.in2.d.d[0]" "t.in2.r" += "t.in2.r" "t.a.in2.r" += "t.in2.a" "t.a.in2.a" += "t.in2.d.d[0]" "t.a.in2.d.d[0]" += "t.in2.d.d[0]" "t.in2.r" diff --git a/test/unit_tests/arbiter_handshake/test.act b/test/unit_tests/arbiter_handshake/test.act index b4685d0..54cb74e 100644 --- a/test/unit_tests/arbiter_handshake/test.act +++ b/test/unit_tests/arbiter_handshake/test.act @@ -33,9 +33,9 @@ open tmpl::dataflow_neuro; defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out) { - arbiter_handshake a(.in1 = in1, .in2 = in, .out = out); + arbiter_handshake a(.in1 = in1, .in2 = in2, .out = out); a.supply.vdd = Vdd; - a.supply.vss = Gnd; + a.supply.vss = GND; } arbiter_test t; \ No newline at end of file diff --git a/test/unit_tests/arbiter_handshake/test.prsim b/test/unit_tests/arbiter_handshake/test.prsim index b17b095..44daaea 100644 --- a/test/unit_tests/arbiter_handshake/test.prsim +++ b/test/unit_tests/arbiter_handshake/test.prsim @@ -1,42 +1,39 @@ watchall cycle -system "echo 'reset done'" -t.in1.d 0 -t.in2.d 0 -t.in1.v 0 -t.in2.v 0 -t.out.a 0 +set t.in1.r 0 +set t.in2.r 0 +set t.out.a 0 cycle status X mode run -system "echo 'step 1.1 finished'" -set a.a 1 -set a.b 1 -advance 1000000 +system "echo '[0] reset done'" + +set t.in1.r 1 +cycle +assert t.out.r 1 +set t.out.a 1 +cycle +assert t.in1.a 1 +system "echo '[1] test in1 done'" + +set t.in1.r 0 +set t.in2.r 0 +set t.out.a 0 +cycle status X mode run -system "echo 'step 1.2 finished'" -set a.a 0 -set a.b 0 -advance 1000000 -status X -mode run -system "echo 'step 2.1 finished'" -set a.a 1 -set a.b 1 -advance 1000000 -status X -mode run -system "echo 'step 2.2 finished'" -set a.a 0 -set a.b 0 -advance 1000000 -status X -mode run -system "echo 'step 3.1 finished'" -set a.a 0 -set a.b 1 -advance 1000000 -status X -mode run -system "echo 'step 3.2 finished'" +assert t.out.r 0 +assert t.in1.a 0 +assert t.in2.a 0 +system "echo '[2] reset done'" + +set t.in2.r 1 +set t.in1.r 0 +set t.out.a 0 +cycle +assert t.out.r 1 +set t.out.a 1 +cycle +assert t.in2.a 1 +system "echo '[3] test in2 done'" +