diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act index 308a8b7..21332ed 100644 --- a/dataflow_neuro/cell_lib_async.act +++ b/dataflow_neuro/cell_lib_async.act @@ -524,6 +524,19 @@ namespace tmpl { mk_excllo(_y1, _y2) } } + defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) + { + prs{ + [keeper=0] a -> y- + } + } + + defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) + { + prs{ + [keeper=0] ~a -> y+ + } + } }} diff --git a/dataflow_neuro/cell_lib_std.act b/dataflow_neuro/cell_lib_std.act index 10ed5fd..89f6dfb 100644 --- a/dataflow_neuro/cell_lib_std.act +++ b/dataflow_neuro/cell_lib_std.act @@ -373,6 +373,49 @@ namespace tmpl { } sizing { _en{-2}; y{-2,2} } } + export defproc DFFQ_R_X1 (bool? clk, reset, S, d, vdd, vss; bool! q) + { + bool _clk, __clk, _q_B, _dl; + bool _Ro, _So; + bool _So2; + bool _qb; + + prs { + _q_B<10> -> q- + ~_q_B<20> -> q+ + + clk<10> -> _clk- + ~clk<20> -> _clk+ + + _clk<10> -> __clk- + ~_clk<20> -> __clk+ + + reset<20> -> _Ro- + ~reset<20> -> _Ro+ + + // S<20> & _dl -> _So- + // ~S<20> | ~_dl -> _So+ + + [keeper=0] d<10> & _clk -> _dl- + ~d<20> & ~__clk<10> -> _dl+ + + reset<20> & _qb -> _q_B- + ~reset<20> | ~_qb -> _q_B+ + + // _q_B<20> & S -> _So2- + // ~_q_B<20> | ~S -> _So2+ + + // input stage feedback + transgate<10> (__clk,_clk,_Ro,_dl) + + // input to output + transgate<10> (__clk,_clk,reset,_qb) + + // output feedback + transgate<10> (_clk,__clk,reset,_qb) + } + sizing { q{-1} } + } } } diff --git a/dataflow_neuro/coders.act b/dataflow_neuro/coders.act index 087fde0..7ad3757 100644 --- a/dataflow_neuro/coders.act +++ b/dataflow_neuro/coders.act @@ -234,7 +234,6 @@ namespace tmpl { } - // Generates the OR-trees required to go from // N one-hot inputs to Nc dual rail binary encoding. export template @@ -282,46 +281,137 @@ namespace tmpl { ) - - - - - } + template + defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2 addr; power supply; bool reset_B) { + // Reset buffers + bool _reset_BX,_reset_BXX[H]; + BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + sigbuf<2*address_size+3> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); - // template - // defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2 addr; bool! out_a; power supply) - // { - // // Arbiters - // a1of1 _out_arb_x,_out_arb_y; - // a1of1 _x_temp[N]; - // (i:N: - // _x_temp[i].r = x[i].r; - // ) - // (i:M: - // _y_temp[i].r = y[i].r; - // ) - // arbtree Xarb(.in = _x_temp,.out = _out_arb_X,.supply = supply); - // arbtree Yarb(.in = _y_temp,.out = _out_arb_Y,.supply = supply); + // Arbiters + a1of1 _out_arb_x,_out_arb_y; + a1of1 _x_temp[N]; + (i:N: + _x_temp[i].r = x[i].r; + ) + (i:M: + _y_temp[i].r = y[i].r; + ) + arbtree Xarb(.in = _x_temp,.out = _out_arb_X,.supply = supply); + arbtree Yarb(.in = _y_temp,.out = _out_arb_Y,.supply = supply); - // sigbuf x_ack_arb[N]; - // sigbuf y_ack_arb[M]; - // (i:N: - // x_ack_arb[i].in = _x_temp[i].a; - // x_ack_arb[i].out[0] = x[i].a; - // x_ack_arb[i].supply = supply; - // ) - // (i:M: - // y_ack_arb[i].in = _y_temp[i].a; - // y_ack_arb[i].out[0] = y[i].a; - // y_ack_arb[i].supply = supply; - // ) + // Sigbufs for strong ackowledge signals + sigbuf_1output x_ack_arb[N]; + sigbuf_1output y_ack_arb[M]; + (i:N: + x_ack_arb[i].in = _x_temp[i].a; + x_ack_arb[i].out[0] = x[i].a; + x_ack_arb[i].supply = supply; + ) + (i:M: + y_ack_arb[i].in = _y_temp[i].a; + y_ack_arb[i].out[0] = y[i].a; + y_ack_arb[i].supply = supply; + ) + // This block checks that the input is valid and that the arbiter made a choice + // Then activates the ack of the arbiter + bool _x_v,_in_x_v; + A_2C2P_RB_X1 Y_ack_confirm(); + Y_ack_confirm.p1 = _x_v; + Y_ack_confirm.p2 =_in_x_v; + Y_ack_confirm.c1 = _out_arb_Y.r; + Y_ack_confirm.c2 = _x_a_B; + Y_ack_confirm.y = _out_arb_Y.a; + Y_ack_confirm.vdd = supply.vdd; + Y_ack_confirm.vss = supply.vss; + Y_ack_confirm.reset_B = _reset_BXX[0]; + + // This block checks that the input is valid and that the arbiter made a choice + // Then activates the ack of the arbiter + A_2C_RB X_ack_confirm(); + X_ack_confirm.c1 = _out_arb_X.r; + X_ack_confirm.c2 = _x_a_B; + X_ack_confirm.vdd = supply.vdd; + X_ack_confirm.vss = supply.vss; + X_ack_confirm.reset_B = _reset_BXX[1]; + + //X_REQ validation + bool _x_req_array[N],_x_v,_x_v_B; + (i:N:_x_req_array[i] = x[i].r;) + ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply); + INV_X1 not_x_req_ortree(.in = _x_v,.out = _x_v_B); + + // + A_2P3P1C2N_RB_X4 x_ack(); + //branch1 + x_ack.p1 = _in_x_v; + x_ack.p2 = _x_v_B; + //branch2 + x_ack.p3 = _in_x_v; + x_ack.p4 = _in_y_v; + x_ack.p5 = _x_v; + // + x_ack.c1 = _en + x_ack.n1 = addr.v + x_ack.n2 = _in_x_v; + // + x_ack.y = _x_a; + // + x_ack.vdd = supply.vdd; + x_ack.vss = supply.vss; + x_ack.reset_B = _reset_BXX[2]; + + INV_X1 not_x_ack(.in = _x_a,.out = _x_a_B); + + A_1C2P enabling(.p1 = addr.a, .p2 = addr.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss) + + avMx1of2 _in_x; + dualrail _in; + _in_x.d = _in.d; + _in_x.v = _in_x_v; + + //buffer_func_s + A_2C2N_RB buffer_func_s_f[address_size]; + A_2C2N_RB buffer_func_s_t[address_size]; + sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); + sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); + INV_X1 out_a_inv(.a=addr.a,.y=_out_a_B); + sigbuf out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply); + sigbuf out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply); + + (i:address_size: + buffer_func_s_f[i].c1 = _en_X_f[i]; + buffer_func_s_f[i].c2 = _out_a_BX_f[i]; + buffer_func_s_f[i].n1 = _in_x.d.d[i].f; + buffer_func_s_f[i].n1 = _in_x.v; + buffer_func_s_f[i].vdd=supply.vdd; + buffer_func_s_f[i].vss=supply.vss; + buffer_func_s_f[i].pr_B = _reset_BXX[i+3]; + buffer_func_s_f[i].sr_B = _reset_BXX[i+3]; + buffer_func_s_f[i].y = addr.d.d[i].f; + + buffer_func_s_t[i].c1 = _en_X_r[i]; + buffer_func_s_t[i].c2 = _out_a_BX_t[i]; + buffer_func_s_t[i].n1 = _in_x.d.d[i].r; + buffer_func_s_t[i].n1 = _in_x.v; + buffer_func_s_t[i].vdd=supply.vdd; + buffer_func_s_t[i].vss=supply.vss; + buffer_func_s_t[i].pr_B = _reset_BXX[i+3+address_size]; + buffer_func_s_t[i].sr_B = _reset_BXX[i+3+address_size]; + buffer_func_s_t[i].y = addr.d.d[i].t; + ) + bool _addr_v + vtree addr_validity(.in = addr,.out = _addr_v); + sigbuf_1output<4> addr_validity_x(.in = _addr_v,.out = addr.v); + addr_validity.supply = supply; + addr_validity_x.supply = supply; + } - // } } diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 7ca5332..fdcb11d 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -673,4 +673,27 @@ namespace tmpl { (i:N:mu2[i].vss = supply.vss;) (i:((1< log2(number of words), parameters you can store +// wl -> word length, length of each word +// N_dly_cfg -> the number of config bits in the ACK delay line +// The block has the pins: +// in -> input data, +// - the first bit is write/read_B +// - the next log_nw bits describe the location, +// - the last wl the word to write +// data -> the data saved in the flip flop, sized wl x nw +export template +defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of data[2< val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply); + in.v = _in_v_temp; + // Generation of the clock pulse + delayprog dly(.in = _in_v_temp, .s = _clock_temp, .supply = supply); + sigbuf_1output<4> val_input_X(.in = _clock_temp,.out = _clock,.supply = supply); + // Sending back to the ackowledge + delayprog dly(.in = _clock, .s = _in_a_temp, .supply = supply); + sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply); + //Reset Buffers + bool _reset_BX,_reset_BXX[_nw*w]; + BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + sigbuf<_nw*wl> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); + // Creating the different flip flop arrays + bool _nw = 2< atree[_nw]; + AND2_X1 and_encoder[_nw] + sigbuf clock_buffer; + DFQ_R_X1 ff[_nw*wl]; + (k:_nw:atree_x[k].supply = supply;) + (_word_idx:_nw: + // Decoding the bit pattern to understand which word we are looking at + (pin_idx:log_nw: + bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j + [bitval = 1 -> + atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t; + [] bitval = 0 -> + atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f; + []bitval >= 2 -> {false : "fuck"}; + ] + ) + // Activating the fake clock for the right word + atree_x[_word_idx].out = _out_encoder[_word_idx]; + and_encoder[_word_idx].a = _out_encoder[_word_idx]; + and_encoder[_word_idx].b = _clock + and_encoder[_word_idx].y = _clock_word_temp[_word_idx]; + and_encoder[_word_idx].vdd = supply.vdd; + and_encoder[_word_idx].vss = supply.vss; + clock_buffer[_word_idx].in = _clock_word_temp[_word_idx]; + clock_buffer[_word_idx].out = _clock_word[_word_idx]; + clock_buffer[_word_idx].vdd = supply.vdd; + clock_buffer[_word_idx].vss = supply.vss; + // Describing all the FF and their connection + (_bit_idx:wl: + ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx]; + ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw]; + ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx]; + ff[_bit_idx*(1+_word_idx)].reset_B = reset_BXX[_bit_idx*(1+_word_idx)]; + ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd; + ff[_bit_idx*(1+_word_idx)].vss = supply.vss; + ) + ) +} +}} + diff --git a/dataflow_neuro/treegates.act b/dataflow_neuro/treegates.act index bf89863..ce2e57b 100644 --- a/dataflow_neuro/treegates.act +++ b/dataflow_neuro/treegates.act @@ -439,6 +439,32 @@ defproc sigbuf (bool? in; bool! out[N]; power supply) (i:1..N-1:out[i]=out[0];) } +//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires. +export template +defproc sigbuf_1output (bool? in; bool! out; power supply) +{ + + { N >= 0 : "sigbuf: parameter error" }; + { N <= 43 : "sigbuf: parameter error, N too big" }; + + /* -- just use in sized driver here -- */ + [ N <= 4 -> + BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 5 & N <= 7 -> + BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 8 & N <= 10 -> + BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 11 & N <= 14 -> + BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 15 & N <= 18 -> + BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 19 & N <= 29 -> + BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + [] N >= 30 & N <= 42 -> + BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + ] +} + }} diff --git a/test/unit_tests/buf_15.v b/test/unit_tests/buf_15.v new file mode 100644 index 0000000..45667dd --- /dev/null +++ b/test/unit_tests/buf_15.v @@ -0,0 +1,685 @@ +// +// Verilog module for: BUF_X6<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a); + output y; + input a; + +// -- signals --- + reg y; + wire a; + reg _y; + +// --- instances +endmodule + +// +// Verilog module for: sigbuf<15> +// +module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] ); + input in; + output \out[0] ; + +// -- signals --- + wire in; + reg \out[0] ; + +// --- instances +_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in)); +endmodule + +// +// Verilog module for: A_3C_RB_X4<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B); + output y; + input c1; + input c2; + input c3; + input pr_B; + input sr_B; + +// -- signals --- + wire sr_B; + wire pr_B; + wire c3; + wire c1; + reg _y; + reg y; + wire c2; + +// --- instances +endmodule + +// +// Verilog module for: BUF_X4<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a); + output y; + input a; + +// -- signals --- + reg _y; + wire a; + reg y; + +// --- instances +endmodule + +// +// Verilog module for: INV_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a); + output y; + input a; + +// -- signals --- + reg y; + wire a; + +// --- instances +endmodule + +// +// Verilog module for: A_2C_B_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2); + output y; + input c1; + input c2; + +// -- signals --- + reg y; + reg _y; + wire c2; + wire c1; + +// --- instances +endmodule + +// +// Verilog module for: A_3C_B_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3); + output y; + input c1; + input c2; + input c3; + +// -- signals --- + reg _y; + reg y; + wire c3; + wire c1; + wire c2; + +// --- instances +endmodule + +// +// Verilog module for: ctree<15> +// +module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out); + input \in[0] ; + input \in[1] ; + input \in[2] ; + input \in[3] ; + input \in[4] ; + input \in[5] ; + input \in[6] ; + input \in[7] ; + input \in[8] ; + input \in[9] ; + input \in[10] ; + input \in[11] ; + input \in[12] ; + input \in[13] ; + input \in[14] ; + output out; + +// -- signals --- + wire \in[4] ; + wire \in[11] ; + wire \in[12] ; + reg \tmp[21] ; + wire \in[3] ; + reg out; + reg \tmp[23] ; + wire \in[6] ; + wire \in[0] ; + reg \tmp[18] ; + wire \in[10] ; + reg \tmp[15] ; + reg \tmp[16] ; + wire \in[13] ; + wire \in[1] ; + wire \in[9] ; + wire \in[2] ; + wire \in[5] ; + reg \tmp[24] ; + wire \in[14] ; + reg \tmp[19] ; + wire \in[7] ; + reg \tmp[22] ; + reg \tmp[20] ; + wire \in[8] ; + reg \tmp[17] ; + +// --- instances +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] )); +endmodule + +// +// Verilog module for: OR2_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b); + output y; + input a; + input b; + +// -- signals --- + reg y; + wire a; + reg _y; + wire b; + +// --- instances +endmodule + +// +// Verilog module for: vtree<15> +// +module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out); + input \in.d[0].d[0] ; + input \in.d[0].d[1] ; + input \in.d[1].d[0] ; + input \in.d[1].d[1] ; + input \in.d[2].d[0] ; + input \in.d[2].d[1] ; + input \in.d[3].d[0] ; + input \in.d[3].d[1] ; + input \in.d[4].d[0] ; + input \in.d[4].d[1] ; + input \in.d[5].d[0] ; + input \in.d[5].d[1] ; + input \in.d[6].d[0] ; + input \in.d[6].d[1] ; + input \in.d[7].d[0] ; + input \in.d[7].d[1] ; + input \in.d[8].d[0] ; + input \in.d[8].d[1] ; + input \in.d[9].d[0] ; + input \in.d[9].d[1] ; + input \in.d[10].d[0] ; + input \in.d[10].d[1] ; + input \in.d[11].d[0] ; + input \in.d[11].d[1] ; + input \in.d[12].d[0] ; + input \in.d[12].d[1] ; + input \in.d[13].d[0] ; + input \in.d[13].d[1] ; + input \in.d[14].d[0] ; + input \in.d[14].d[1] ; + output out; + +// -- signals --- + reg \ct.in[14] ; + reg \ct.in[13] ; + wire \in.d[7].d[0] ; + wire \in.d[1].d[0] ; + wire \in.d[0].d[0] ; + reg \ct.in[4] ; + reg out; + wire \in.d[10].d[0] ; + wire \in.d[4].d[1] ; + reg \ct.in[3] ; + wire \in.d[9].d[1] ; + wire \in.d[1].d[1] ; + wire \in.d[2].d[0] ; + wire \in.d[10].d[1] ; + reg \ct.in[8] ; + wire \in.d[12].d[0] ; + wire \in.d[5].d[0] ; + wire \in.d[4].d[0] ; + reg \ct.in[10] ; + reg \ct.in[0] ; + wire \in.d[11].d[0] ; + wire \in.d[7].d[1] ; + wire \in.d[3].d[1] ; + reg \ct.in[11] ; + reg \ct.in[2] ; + reg \ct.in[9] ; + wire \in.d[13].d[0] ; + wire \in.d[14].d[1] ; + wire \in.d[11].d[1] ; + wire \in.d[13].d[1] ; + wire \in.d[0].d[1] ; + reg \ct.in[1] ; + wire \in.d[14].d[0] ; + wire \in.d[12].d[1] ; + wire \in.d[9].d[0] ; + wire \in.d[2].d[1] ; + reg \ct.in[5] ; + wire \in.d[5].d[1] ; + reg \ct.in[12] ; + reg \ct.in[6] ; + wire \in.d[3].d[0] ; + wire \in.d[8].d[0] ; + wire \in.d[8].d[1] ; + reg \ct.in[7] ; + wire \in.d[6].d[0] ; + wire \in.d[6].d[1] ; + +// --- instances +_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out)); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] )); +endmodule + +// +// Verilog module for: A_1C1P_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1); + output y; + input c1; + input p1; + +// -- signals --- + reg y; + wire c1; + wire p1; + +// --- instances +endmodule + +// +// Verilog module for: BUF_X1<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a); + output y; + input a; + +// -- signals --- + reg y; + wire a; + reg _y; + +// --- instances +endmodule + +// +// Verilog module for: A_2C1N_RB_X4<> +// +module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B); + output y; + input c1; + input c2; + input n1; + input pr_B; + input sr_B; + +// -- signals --- + reg y; + wire pr_B; + wire c2; + wire n1; + wire c1; + reg _y; + wire sr_B; + +// --- instances +endmodule + +// +// Verilog module for: buffer<15> +// +module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B); + input \in.d.d[0].d[0] ; + input \in.d.d[0].d[1] ; + input \in.d.d[1].d[0] ; + input \in.d.d[1].d[1] ; + input \in.d.d[2].d[0] ; + input \in.d.d[2].d[1] ; + input \in.d.d[3].d[0] ; + input \in.d.d[3].d[1] ; + input \in.d.d[4].d[0] ; + input \in.d.d[4].d[1] ; + input \in.d.d[5].d[0] ; + input \in.d.d[5].d[1] ; + input \in.d.d[6].d[0] ; + input \in.d.d[6].d[1] ; + input \in.d.d[7].d[0] ; + input \in.d.d[7].d[1] ; + input \in.d.d[8].d[0] ; + input \in.d.d[8].d[1] ; + input \in.d.d[9].d[0] ; + input \in.d.d[9].d[1] ; + input \in.d.d[10].d[0] ; + input \in.d.d[10].d[1] ; + input \in.d.d[11].d[0] ; + input \in.d.d[11].d[1] ; + input \in.d.d[12].d[0] ; + input \in.d.d[12].d[1] ; + input \in.d.d[13].d[0] ; + input \in.d.d[13].d[1] ; + input \in.d.d[14].d[0] ; + input \in.d.d[14].d[1] ; + output \in.a ; + output \in.v ; + output \out.d.d[0].d[0] ; + output \out.d.d[0].d[1] ; + output \out.d.d[1].d[0] ; + output \out.d.d[1].d[1] ; + output \out.d.d[2].d[0] ; + output \out.d.d[2].d[1] ; + output \out.d.d[3].d[0] ; + output \out.d.d[3].d[1] ; + output \out.d.d[4].d[0] ; + output \out.d.d[4].d[1] ; + output \out.d.d[5].d[0] ; + output \out.d.d[5].d[1] ; + output \out.d.d[6].d[0] ; + output \out.d.d[6].d[1] ; + output \out.d.d[7].d[0] ; + output \out.d.d[7].d[1] ; + output \out.d.d[8].d[0] ; + output \out.d.d[8].d[1] ; + output \out.d.d[9].d[0] ; + output \out.d.d[9].d[1] ; + output \out.d.d[10].d[0] ; + output \out.d.d[10].d[1] ; + output \out.d.d[11].d[0] ; + output \out.d.d[11].d[1] ; + output \out.d.d[12].d[0] ; + output \out.d.d[12].d[1] ; + output \out.d.d[13].d[0] ; + output \out.d.d[13].d[1] ; + output \out.d.d[14].d[0] ; + output \out.d.d[14].d[1] ; + input \out.a ; + input \out.v ; + input reset_B; + +// -- signals --- + reg \out.d.d[8].d[0] ; + reg \out.d.d[6].d[1] ; + reg \out.d.d[5].d[1] ; + reg \_en_X_f[0] ; + wire \in.d.d[14].d[0] ; + wire \in.d.d[12].d[1] ; + reg \out.d.d[12].d[1] ; + wire \in.d.d[5].d[0] ; + reg \out.d.d[11].d[0] ; + reg \out.d.d[7].d[0] ; + reg _reset_BX; + reg \_reset_BXX[0] ; + wire \in.d.d[14].d[1] ; + wire \in.d.d[10].d[1] ; + wire \in.d.d[2].d[0] ; + wire \out.a ; + reg \out.d.d[0].d[0] ; + wire \in.d.d[0].d[0] ; + reg \out.d.d[10].d[1] ; + wire \in.d.d[11].d[0] ; + wire \in.d.d[7].d[1] ; + wire \in.d.d[3].d[1] ; + reg _in_v; + reg \in.v ; + reg _out_a_B; + wire \in.d.d[9].d[1] ; + wire \in.d.d[9].d[0] ; + wire \in.d.d[4].d[1] ; + reg \out.d.d[10].d[0] ; + wire \in.d.d[1].d[1] ; + wire \in.d.d[12].d[0] ; + wire \in.d.d[1].d[0] ; + reg \_out_a_BX_f[0] ; + reg \out.d.d[3].d[1] ; + reg \out.d.d[0].d[1] ; + reg \out.d.d[2].d[1] ; + reg \out.d.d[4].d[1] ; + wire reset_B; + wire \in.d.d[8].d[0] ; + reg \out.d.d[12].d[0] ; + wire \in.d.d[5].d[1] ; + reg \out.d.d[9].d[0] ; + reg \out.d.d[7].d[1] ; + reg \_out_a_BX_t[0] ; + wire \in.d.d[10].d[0] ; + reg \out.d.d[1].d[0] ; + wire \in.d.d[6].d[0] ; + wire \in.d.d[7].d[0] ; + wire \in.d.d[13].d[1] ; + wire \out.v ; + reg \out.d.d[2].d[0] ; + wire \in.d.d[13].d[0] ; + wire \in.d.d[11].d[1] ; + wire \in.d.d[6].d[1] ; + reg \out.d.d[3].d[0] ; + reg \out.d.d[11].d[1] ; + reg \out.d.d[9].d[1] ; + wire \in.d.d[3].d[0] ; + reg _en; + reg \out.d.d[13].d[0] ; + reg \out.d.d[5].d[0] ; + reg \in.a ; + reg \out.d.d[14].d[0] ; + reg \out.d.d[4].d[0] ; + wire \in.d.d[8].d[1] ; + reg \out.d.d[13].d[1] ; + reg \out.d.d[8].d[1] ; + reg \out.d.d[14].d[1] ; + wire \in.d.d[2].d[1] ; + reg \out.d.d[6].d[0] ; + wire \in.d.d[4].d[0] ; + reg \out.d.d[1].d[1] ; + reg \_en_X_t[0] ; + wire \in.d.d[0].d[1] ; + +// --- instances +_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX)); +_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v)); +_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a )); +_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v)); +_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v )); +_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B)); +_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] )); +endmodule + +// +// Verilog module for: buffer_15<> +// +module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v ); + input \in.d.d[0].d[0] ; + input \in.d.d[0].d[1] ; + input \in.d.d[1].d[0] ; + input \in.d.d[1].d[1] ; + input \in.d.d[2].d[0] ; + input \in.d.d[2].d[1] ; + input \in.d.d[3].d[0] ; + input \in.d.d[3].d[1] ; + input \in.d.d[4].d[0] ; + input \in.d.d[4].d[1] ; + input \in.d.d[5].d[0] ; + input \in.d.d[5].d[1] ; + input \in.d.d[6].d[0] ; + input \in.d.d[6].d[1] ; + input \in.d.d[7].d[0] ; + input \in.d.d[7].d[1] ; + input \in.d.d[8].d[0] ; + input \in.d.d[8].d[1] ; + input \in.d.d[9].d[0] ; + input \in.d.d[9].d[1] ; + input \in.d.d[10].d[0] ; + input \in.d.d[10].d[1] ; + input \in.d.d[11].d[0] ; + input \in.d.d[11].d[1] ; + input \in.d.d[12].d[0] ; + input \in.d.d[12].d[1] ; + input \in.d.d[13].d[0] ; + input \in.d.d[13].d[1] ; + input \in.d.d[14].d[0] ; + input \in.d.d[14].d[1] ; + output \in.a ; + output \in.v ; + output \out.d.d[0].d[0] ; + output \out.d.d[0].d[1] ; + output \out.d.d[1].d[0] ; + output \out.d.d[1].d[1] ; + output \out.d.d[2].d[0] ; + output \out.d.d[2].d[1] ; + output \out.d.d[3].d[0] ; + output \out.d.d[3].d[1] ; + output \out.d.d[4].d[0] ; + output \out.d.d[4].d[1] ; + output \out.d.d[5].d[0] ; + output \out.d.d[5].d[1] ; + output \out.d.d[6].d[0] ; + output \out.d.d[6].d[1] ; + output \out.d.d[7].d[0] ; + output \out.d.d[7].d[1] ; + output \out.d.d[8].d[0] ; + output \out.d.d[8].d[1] ; + output \out.d.d[9].d[0] ; + output \out.d.d[9].d[1] ; + output \out.d.d[10].d[0] ; + output \out.d.d[10].d[1] ; + output \out.d.d[11].d[0] ; + output \out.d.d[11].d[1] ; + output \out.d.d[12].d[0] ; + output \out.d.d[12].d[1] ; + output \out.d.d[13].d[0] ; + output \out.d.d[13].d[1] ; + output \out.d.d[14].d[0] ; + output \out.d.d[14].d[1] ; + input \out.a ; + input \out.v ; + +// -- signals --- + reg \out.d.d[2].d[1] ; + wire \in.d.d[10].d[0] ; + reg \out.d.d[1].d[0] ; + wire \in.d.d[10].d[1] ; + wire \in.d.d[4].d[0] ; + reg \out.d.d[10].d[1] ; + wire \in.d.d[13].d[0] ; + reg \out.d.d[13].d[0] ; + reg \out.d.d[9].d[1] ; + wire \in.d.d[2].d[1] ; + reg \out.d.d[2].d[0] ; + reg \out.d.d[0].d[0] ; + reg \out.d.d[14].d[0] ; + reg \out.d.d[5].d[0] ; + reg \in.a ; + reg _reset_B; + wire \out.v ; + wire \out.a ; + reg \out.d.d[4].d[0] ; + wire \in.d.d[9].d[1] ; + wire \in.d.d[3].d[0] ; + wire \in.d.d[11].d[0] ; + wire \in.d.d[2].d[0] ; + reg \out.d.d[6].d[0] ; + reg \out.d.d[13].d[1] ; + reg \out.d.d[10].d[0] ; + reg \out.d.d[7].d[1] ; + wire \in.d.d[12].d[1] ; + wire \in.d.d[6].d[1] ; + reg \out.d.d[7].d[0] ; + reg \out.d.d[3].d[0] ; + wire \in.d.d[1].d[0] ; + reg \out.d.d[14].d[1] ; + reg \out.d.d[8].d[0] ; + wire \in.d.d[13].d[1] ; + wire \in.d.d[7].d[0] ; + reg \out.d.d[12].d[0] ; + wire \in.d.d[8].d[1] ; + reg \out.d.d[4].d[1] ; + wire \in.d.d[14].d[0] ; + wire \in.d.d[5].d[1] ; + wire \in.d.d[1].d[1] ; + wire \in.d.d[9].d[0] ; + wire \in.d.d[14].d[1] ; + reg \out.d.d[11].d[0] ; + reg \out.d.d[6].d[1] ; + wire \in.d.d[12].d[0] ; + wire \in.d.d[7].d[1] ; + reg \out.d.d[0].d[1] ; + wire \in.d.d[11].d[1] ; + wire \in.d.d[8].d[0] ; + wire \in.d.d[5].d[0] ; + reg \out.d.d[1].d[1] ; + reg \in.v ; + wire \in.d.d[0].d[1] ; + wire \in.d.d[0].d[0] ; + reg \out.d.d[5].d[1] ; + reg \out.d.d[8].d[1] ; + reg \out.d.d[3].d[1] ; + wire \in.d.d[6].d[0] ; + reg \out.d.d[11].d[1] ; + wire \in.d.d[3].d[1] ; + reg \out.d.d[12].d[1] ; + wire \in.d.d[4].d[1] ; + reg \out.d.d[9].d[0] ; + +// --- instances +_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B)); +endmodule + diff --git a/test/unit_tests/flipflop/run/prsim.out b/test/unit_tests/flipflop/run/prsim.out new file mode 100644 index 0000000..c5d4588 --- /dev/null +++ b/test/unit_tests/flipflop/run/prsim.out @@ -0,0 +1,9 @@ +t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk +[0] start test + +[1] reset completed +WRONG ASSERT: "t.q" has value 1 and not 0. +[2] setting d to 1 +WRONG ASSERT: "t.q" has value 1 and not 0. +[3] setting clk to 1 +[4] Finished diff --git a/test/unit_tests/flipflop/run/test.prs b/test/unit_tests/flipflop/run/test.prs new file mode 100644 index 0000000..b3bfd09 --- /dev/null +++ b/test/unit_tests/flipflop/run/test.prs @@ -0,0 +1,29 @@ += "GND" "GND" += "Vdd" "Vdd" += "Reset" "Reset" +"Reset"->"t._reset_B"- +~("Reset")->"t._reset_B"+ +"t.ff._q_B"->"t.ff.q"- +~"t.ff._q_B"->"t.ff.q"+ +"t.ff.clk"->"t.ff._clk"- +~"t.ff.clk"->"t.ff._clk"+ +"t.ff._clk"->"t.ff.__clk"- +~"t.ff._clk"->"t.ff.__clk"+ +"t.ff.reset"->"t.ff._Ro"- +~"t.ff.reset"->"t.ff._Ro"+ +"t.ff.d"&"t.ff._clk"->"t.ff._dl"- +~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+ +"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"- +~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+ +after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"- +~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+ +after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"- +~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+ +after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"- +~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+ += "Reset" "t.ff.reset" += "Vdd" "t.ff.vdd" += "GND" "t.ff.vss" += "t.q" "t.ff.q" += "t.clk" "t.ff.clk" += "t.d" "t.ff.d" diff --git a/test/unit_tests/flipflop/test.act b/test/unit_tests/flipflop/test.act new file mode 100644 index 0000000..1b03039 --- /dev/null +++ b/test/unit_tests/flipflop/test.act @@ -0,0 +1,48 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/primitives.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc flipflop_test (bool! q; bool? d,clk){ + + DFFQ_R_X1 ff(.d=d,.clk = clk, .q = q); + //Low active Reset + bool _reset_B; + prs { + Reset => _reset_B- + } + ff.vss = GND; + ff.vdd = Vdd; + ff.reset = Reset; + +} + +flipflop_test t; diff --git a/test/unit_tests/flipflop/test.prsim b/test/unit_tests/flipflop/test.prsim new file mode 100644 index 0000000..3cc8281 --- /dev/null +++ b/test/unit_tests/flipflop/test.prsim @@ -0,0 +1,21 @@ + +set t.d 0 +set t.clk 0 +set Reset 0 +cycle +assert t.q 0 +system "echo '[0] start test'" +set Reset 1 +cycle +status X +mode run +system "echo '[1] reset completed'" +system "echo '[2] setting d to 1'" +set t.clk 1 +cycle +assert t.q 0 +system "echo '[3] setting clk to 1'" +set t.clk 1 +cycle +assert t.q 1 +system "echo '[4] Finished'" diff --git a/test/unit_tests/line_end_pull_up/run/prsim.out b/test/unit_tests/line_end_pull_up/run/prsim.out new file mode 100644 index 0000000..19befb5 --- /dev/null +++ b/test/unit_tests/line_end_pull_up/run/prsim.out @@ -0,0 +1,17 @@ +t.in.a t.lepu.nor_out t.lepu.__out t.lepu.buf1._y t.lepu._out t.out t.lepu.buf2._y + 1 t.in.a : 0 + 7093 t.lepu.buf1._y : 1 [by t.in.a:=0] + 17560 t.lepu._out : 0 [by t.lepu.buf1._y:=1] + 17562 t.lepu.nor_out : 1 [by t.lepu._out:=0] + 22313 t.lepu.buf2._y : 1 [by t.lepu._out:=0] + 23450 t.lepu.__out : 0 [by t.lepu.buf2._y:=1] +yo man + 23450 Reset : 0 + 23564 t._reset_B : 1 [by Reset:=0] + 88930 t.lepu.nor_out : 0 [by t._reset_B:=1] + 90656 t.out : 1 [by t.lepu.nor_out:=0] + 90656 t.in.a : 1 + 90695 t.lepu.buf1._y : 0 [by t.in.a:=1] + 90710 t.lepu._out : 1 [by t.lepu.buf1._y:=0] + 91201 t.lepu.buf2._y : 0 [by t.lepu._out:=1] + 91214 t.lepu.__out : 1 [by t.lepu.buf2._y:=0] diff --git a/test/unit_tests/line_end_pull_up/run/test.prs b/test/unit_tests/line_end_pull_up/run/test.prs new file mode 100644 index 0000000..1dc46af --- /dev/null +++ b/test/unit_tests/line_end_pull_up/run/test.prs @@ -0,0 +1,42 @@ += "GND" "GND" += "Vdd" "Vdd" += "Reset" "Reset" +"Reset"->"t._reset_B"- +~("Reset")->"t._reset_B"+ += "t._reset_B" "t.lepu.reset_B" +~"t.lepu.pull_up.a"->"t.lepu.pull_up.y"+ +"t.lepu.aenor.a"|"t.lepu.aenor.b"->"t.lepu.aenor.y"- +~("t.lepu.aenor.a"|"t.lepu.aenor.b")->"t.lepu.aenor.y"+ += "t.lepu._out" "t.lepu.aenor.a" += "t.lepu._out" "t.lepu.buf2.a" += "t.lepu._out" "t.lepu.buf1.y" += "t.lepu.nor_out" "t.lepu.pull_up.a" += "t.lepu.nor_out" "t.lepu.aenor.y" +"t.lepu.buf1.a"->"t.lepu.buf1._y"- +~("t.lepu.buf1.a")->"t.lepu.buf1._y"+ +"t.lepu.buf1._y"->"t.lepu.buf1.y"- +~("t.lepu.buf1._y")->"t.lepu.buf1.y"+ += "t.lepu.reset_B" "t.lepu.aenor.b" += "t.lepu.supply.vdd" "t.lepu.aenor.vdd" += "t.lepu.supply.vdd" "t.lepu.buf2.vdd" += "t.lepu.supply.vdd" "t.lepu.buf1.vdd" += "t.lepu.supply.vss" "t.lepu.aenor.vss" += "t.lepu.supply.vss" "t.lepu.buf2.vss" += "t.lepu.supply.vss" "t.lepu.buf1.vss" += "t.lepu.__out" "t.lepu.buf2.y" +"t.lepu.buf2.a"->"t.lepu.buf2._y"- +~("t.lepu.buf2.a")->"t.lepu.buf2._y"+ +"t.lepu.buf2._y"->"t.lepu.buf2.y"- +~("t.lepu.buf2._y")->"t.lepu.buf2.y"+ += "t.lepu.in.d.d[0]" "t.lepu.in.r" += "t.lepu.in.a" "t.lepu.buf1.a" += "t.lepu.in.d.d[0]" "t.lepu.in.r" += "t.lepu.out" "t.lepu.pull_up.y" += "Vdd" "t.lepu.supply.vdd" += "GND" "t.lepu.supply.vss" += "t.out" "t.lepu.out" += "t.in.d.d[0]" "t.in.r" += "t.in.r" "t.lepu.in.r" += "t.in.a" "t.lepu.in.a" += "t.in.d.d[0]" "t.lepu.in.d.d[0]" += "t.in.d.d[0]" "t.in.r" diff --git a/test/unit_tests/line_end_pull_up/test.act b/test/unit_tests/line_end_pull_up/test.act new file mode 100644 index 0000000..109d5ad --- /dev/null +++ b/test/unit_tests/line_end_pull_up/test.act @@ -0,0 +1,48 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/primitives.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc lepu (a1of1 in; bool! out){ + + line_end_pull_up lepu(.in=in, .out=out); + //Low active Reset + bool _reset_B; + prs { + Reset => _reset_B- + } + lepu.supply.vss = GND; + lepu.supply.vdd = Vdd; + lepu.reset_B = _reset_B; + +} + +lepu t; diff --git a/test/unit_tests/line_end_pull_up/test.prsim b/test/unit_tests/line_end_pull_up/test.prsim new file mode 100644 index 0000000..29b0358 --- /dev/null +++ b/test/unit_tests/line_end_pull_up/test.prsim @@ -0,0 +1,15 @@ +watchall + +set t.in.a 0 +cycle + +system "echo 'yo man'" + +set Reset 0 +cycle + + +set t.in.a 1 +cycle + +assert t.out 1