From 4dcd9755540b0e3c6451eda0234ab88a64d56d25 Mon Sep 17 00:00:00 2001 From: Michele Date: Wed, 9 Mar 2022 20:02:41 +0100 Subject: [PATCH] register_rw continued --- dataflow_neuro/registers.act | 16 +- test/unit_tests/register_wrw/run/prsim.out | 512 ++++++++++----------- test/unit_tests/register_wrw/run/test.prs | 240 +++++----- test/unit_tests/register_wrw/test.prsim | 26 +- 4 files changed, 380 insertions(+), 414 deletions(-) diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index eb9b80d..0ea0419 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -133,12 +133,8 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2 out; d1of d //Validation of the input avMx1of2 _in_temp2,_in_read,_in_write; avMx1of2<1>_in_flag; - // bool _in_stable; - // (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];) - // vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply); - // sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply); // Read or write? - AND3_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.c = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss); + AND2_X1 ack_and(.a = _in_temp2.a,.b = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss); in.v = _in_temp2.v; _in_flag.d.d[0] = in.d.d[lognw+wl]; (i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];) @@ -148,8 +144,9 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2 out; d1of d // Validation Mx1of2 _in_write_temp; (i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];) - vtree val_input(.in = _in_write_temp,.out = _in_write.v, .supply = supply); - + vtree val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply); + // Acknowledgment + //delayprog ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply); // Generation of the fake clock pulse (inverted because the ff clocks are low_active) delayprog clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply); INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss); @@ -162,11 +159,12 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2 out; d1of d vtree ff_validator; Mx1of2 _out_temp; (i:wl:_out_temp.d[i] = out.d.d[i];) - ff_validator.in = _out_temp; - ff_validator.out = _ff_v; ff_validator.supply = supply; + // Acknowledgment + _in_read.a = _ff_v; //The circuit is ack when flip flop data are valid + //Reset Buffers bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2]; BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); diff --git a/test/unit_tests/register_wrw/run/prsim.out b/test/unit_tests/register_wrw/run/prsim.out index 3c7d42f..83ccfd8 100644 --- a/test/unit_tests/register_wrw/run/prsim.out +++ b/test/unit_tests/register_wrw/run/prsim.out @@ -1,275 +1,243 @@ -t.registers.read_write_demux.vc.ct.in[0] t.registers._clock_word_temp[0] t.registers.ff_f[4].clk_B t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.atree[2].in[1] t.registers.read_write_demux._in_v t.registers.read_write_demux._c_v t.registers.reading_activator_f[0].a t.registers.ff_t[0].d t.registers.ff_f[4].__clk_B t.registers.ff_t[0]._clk_B t.registers.ff_f[5]._clk_B t.registers.atree[0].in[1] t.registers.atree[0].in[0] t.registers.ff_f[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers._out_encoder[2] t.registers.read_write_demux._out1_a_BX_t[0] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.ff_t[1]._clk_B t.registers.ff_f[0].d t.registers.atree[1].in[0] t.in.v t.registers.ff_t[4]._clk_B t.registers.ff_t[1].d t.registers.ff_f[0].clk_B t.registers.read_write_demux._out1_a_B t.registers.read_write_demux._c_t_buf[0] t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.read_write_demux._out1_a_BX_f[0] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ff_f[1].d t.registers.ff_t[5]._clk_B t.registers.ff_t[4].__clk_B t.registers.reading_activator_t[0].a t.registers.clk_X.buf1._y t.registers.read_write_demux._c_f_buf[0] t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers._out_encoder[3] t.registers.read_write_demux.vc.ct.in[1] t.registers.clk_dly.dly[1]._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.ff_t[0].__clk_B t.registers.ff_t[2]._clk_B t.registers.ff_val[1]._y t.registers.read_write_demux.vc.ct.in[2] t.registers._clock_word_temp[1] t.registers.clk_dly.mu2[0]._s t.registers.clock_buffer[2].buf1._y t.registers.ff_t[1].__clk_B t.registers.read_write_demux.in_v_buf._y t.registers.read_write_demux.out1_a_B_buf_f.buf1._y t.registers.clk_dly.dly[1].__y t.registers.ff_f[7]._clk_B t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.and_encoder[0]._y t.registers.clk_dly._a[1] t.registers.read_write_demux._in_c_v_ t.registers.ff_f[2].__clk_B t.registers.read_write_demux.vc.ct.in[3] t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.c_el._y t.registers.ff_f[7].__clk_B t.registers._in_read.a t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers._clock_word_temp[2] t.registers.atree[2].and2s[0]._y t.registers.ff_f[0].__clk_B t.registers._in_write.a t.registers.ff_val[0].y t.registers.ff_t[6]._clk_B t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.ff_f[4]._clk_B t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.ff_f[2].clk_B t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.read_write_demux.vc.ct.tmp[5] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.clk_dly.dly[1].y t.registers.ff_f[2]._clk_B t.registers.clk_dly.dly[2].y t.registers.read_write_demux.c_buf_f.buf1._y t.registers.ff_val[1].b t.registers.read_write_demux.out1_a_B_buf_t.buf1._y t.registers.ff_val[0].a t.registers.ff_t[2].__clk_B t.registers.atree[1].and2s[0]._y t.registers.ff_f[3].__clk_B t.registers.ff_f[6].__clk_B t.registers.and_encoder[2]._y t.registers.ff_f[6]._clk_B t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_f[0]._clk_B t.registers.read_write_demux.c_buf_t.buf1._y t.registers.ff_val[1].a t.registers.ff_t[3]._clk_B t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.ff_f[1]._clk_B t.registers.ff_val[0]._y t.registers.ff_t[7].__clk_B t.registers.ff_t[7]._clk_B t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.ff_f[5].__clk_B t.registers.ff_f[1].__clk_B t.registers.and_encoder[1]._y t.registers.ff_t[5].__clk_B t.registers.ff_t[6].__clk_B t.registers.and_encoder[3]._y t.registers.read_write_demux.vc.OR2_tf[3]._y t.registers.ff_t[3].__clk_B t.registers.ff_f[3]._clk_B +t.registers.read_write_demux.vc.ct.in[0] t.registers.ff_f[4].clk_B t.registers._clock_word_temp[0] t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.atree[2].in[1] t.registers.read_write_demux._in_v t.registers.read_write_demux._c_v t.registers.reading_activator_f[0].a t.registers.ff_t[0].d t.registers.ff_f[4].__clk_B t.registers.ff_t[0]._clk_B t.registers.ff_f[5]._clk_B t.registers.atree[0].in[1] t.registers.atree[0].in[0] t.registers.ff_f[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers._out_encoder[2] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.ff_t[1]._clk_B t.registers.ff_f[0].d t.registers.atree[1].in[0] t.in.v t.registers.ff_t[4]._clk_B t.registers.ff_t[1].d t.registers.ff_f[0].clk_B t.registers.read_write_demux._c_t_buf[0] t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ff_f[1].d t.registers.ff_t[5]._clk_B t.registers.ff_t[4].__clk_B t.registers.reading_activator_t[0].a t.registers.clk_X.buf1._y t.registers.read_write_demux._c_f_buf[0] t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers._out_encoder[3] t.registers.read_write_demux.vc.ct.in[1] t.registers.clk_dly.dly[1]._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.ff_t[0].__clk_B t.registers.ff_t[2]._clk_B t.registers.ff_val[1]._y t.registers.read_write_demux.vc.ct.in[2] t.registers._clock_word_temp[1] t.registers.clk_dly.mu2[0]._s t.registers.clock_buffer[2].buf1._y t.registers.ff_t[1].__clk_B t.registers.read_write_demux.in_v_buf._y t.registers.clk_dly.dly[1].__y t.registers.ff_f[7]._clk_B t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.and_encoder[0]._y t.registers.clk_dly._a[1] t.registers.read_write_demux._in_c_v_ t.registers.ff_f[2].__clk_B t.registers.read_write_demux.vc.ct.in[3] t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.c_el._y t.registers.ff_f[7].__clk_B t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers._clock_word_temp[2] t.registers.atree[2].and2s[0]._y t.registers.ff_f[0].__clk_B t.registers._in_write.a t.registers.ff_val[0].y t.registers.ff_t[6]._clk_B t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.ff_f[4]._clk_B t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.ff_f[2].clk_B t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.read_write_demux.vc.ct.tmp[5] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.clk_dly.dly[1].y t.registers.ff_f[2]._clk_B t.registers.clk_dly.dly[2].y t.registers.read_write_demux.c_buf_f.buf1._y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.ff_t[2].__clk_B t.registers.atree[1].and2s[0]._y t.registers.ff_f[3].__clk_B t.registers.ff_f[6].__clk_B t.registers.and_encoder[2]._y t.registers.ff_f[6]._clk_B t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_f[0]._clk_B t.registers.read_write_demux.c_buf_t.buf1._y t.registers.ff_val[1].a t.registers.ff_t[3]._clk_B t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.ff_f[1]._clk_B t.registers.ff_val[0]._y t.registers.ff_t[7].__clk_B t.registers.ff_t[7]._clk_B t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.ff_f[5].__clk_B t.registers.ff_f[1].__clk_B t.registers.and_encoder[1]._y t.registers.ff_t[5].__clk_B t.registers.ff_t[6].__clk_B t.registers.and_encoder[3]._y t.registers.read_write_demux.vc.OR2_tf[3]._y t.registers.ff_t[3].__clk_B t.registers.ff_f[3]._clk_B [0] start test -Node `t._in_write.d.d[0].f' not found -Node `t._in_read.d.d[0].f' not found - 250599 t.registers.ff_f[0].d : 0 - 250599 Reset : 0 - 250599 t.registers._in_read.a : 0 - 250599 t.registers.ff_f[1].d : 0 - 250599 t.registers.atree[0].in[1] : 0 - 250599 t.registers._in_write.a : 0 - 250599 t.registers.atree[1].in[0] : 0 - 250599 t.registers.ff_t[0].d : 0 - 250599 t.registers.atree[0].in[0] : 0 - 250599 t.registers.reading_activator_t[0].a : 0 - 250599 t.registers.ff_t[1].d : 0 - 250599 t.registers.reading_activator_f[0].a : 0 - 250599 t.registers.atree[2].in[1] : 0 - 250600 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.registers.ff_t[1].d:=0] - 250602 t.registers.read_write_demux._out1_a_B : 1 [by t.registers._in_read.a:=0] - 250603 t.registers.read_write_demux.c_buf_f.buf1._y : 1 [by t.registers.reading_activator_f[0].a:=0] - 250603 t.registers.read_write_demux.out1_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1] - 250647 t._reset_B : 1 [by Reset:=0] - 250659 t.registers.reset_buf_BXX._y : 0 [by t._reset_B:=1] - 250672 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.registers.reading_activator_f[0].a:=0] - 250673 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1] - 250696 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1] - 250738 t.registers.read_write_demux.out1_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1] - 250772 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] - 250777 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 250778 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] - 250783 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.registers.reading_activator_t[0].a:=0] - 250794 t.registers.read_write_demux._out1_a_BX_t[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_f.buf1._y:=0] - 250815 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0] - 250816 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] - 250844 t.registers.read_write_demux._out1_a_BX_f[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_t.buf1._y:=0] - 251426 t.registers.atree[2].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0] - 251688 t.registers._reset_mem_BX : 1 [by t.registers.reset_buf_BXX._y:=0] - 251701 t.registers.reset_bufarray.buf6._y : 0 [by t.registers._reset_mem_BX:=1] - 253118 t.registers._out_encoder[2] : 0 [by t.registers.atree[2].and2s[0]._y:=1] - 253475 t.registers.and_encoder[2]._y : 1 [by t.registers._out_encoder[2]:=0] - 253500 t.registers._clock_word_temp[2] : 0 [by t.registers.and_encoder[2]._y:=1] - 253521 t.registers.clock_buffer[2].buf1._y : 1 [by t.registers._clock_word_temp[2]:=0] - 253522 t.registers.ff_f[4].clk_B : 0 [by t.registers.clock_buffer[2].buf1._y:=1] - 253523 t.registers.ff_f[5]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0] - 253523 t.registers.ff_t[4]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0] - 253528 t.registers.ff_t[4].__clk_B : 0 [by t.registers.ff_t[4]._clk_B:=1] - 253683 t.registers.ff_t[5]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0] - 254264 t.registers.ff_t[5].__clk_B : 0 [by t.registers.ff_t[5]._clk_B:=1] - 254380 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] - 254547 t.registers.read_write_demux.reset_buf._y : 0 [by t._reset_B:=1] - 254558 t.registers.read_write_demux._reset_BX : 1 [by t.registers.read_write_demux.reset_buf._y:=0] - 254560 t.registers.ff_f[5].__clk_B : 0 [by t.registers.ff_f[5]._clk_B:=1] - 254606 t.registers.reset_buf_BX._y : 0 [by t._reset_B:=1] - 254620 t.registers._reset_BX : 1 [by t.registers.reset_buf_BX._y:=0] - 254788 t.registers.ff_f[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1] - 254792 t.registers.ff_f[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 254806 t.registers.ff_f[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 254892 t.registers.ff_t[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 255120 t.registers.ff_t[0].__clk_B : 0 [by t.registers.ff_t[0]._clk_B:=1] - 255605 t.registers.read_write_demux.reset_bufarray.buf3._y : 0 [by t.registers.read_write_demux._reset_BX:=1] - 255996 t.registers.ff_f[1].__clk_B : 0 [by t.registers.ff_f[1]._clk_B:=1] - 256448 t.registers.read_write_demux._reset_BXX[0] : 1 [by t.registers.read_write_demux.reset_bufarray.buf3._y:=0] - 256550 t.registers.atree[3].and2s[0]._y : 1 [by t.registers.atree[1].in[0]:=0] - 258009 t.registers._out_encoder[3] : 0 [by t.registers.atree[3].and2s[0]._y:=1] - 258079 t.registers.and_encoder[3]._y : 1 [by t.registers._out_encoder[3]:=0] - 262498 t.registers.read_write_demux._out2_a_B : 1 [by t.registers._in_write.a:=0] - 262501 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1] - 262509 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1] - 262555 t.registers.read_write_demux._out2_a_BX_t[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=0] - 263170 t.registers.ff_f[4]._clk_B : 1 [by t.registers.ff_f[4].clk_B:=0] - 263261 t.registers.ff_f[0].__clk_B : 0 [by t.registers.ff_f[0]._clk_B:=1] - 263657 t.registers.read_write_demux._out2_a_BX_f[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=0] - 264331 t.registers.ff_f[4].__clk_B : 0 [by t.registers.ff_f[4]._clk_B:=1] - 268685 t.registers._reset_mem_BXX[0] : 1 [by t.registers.reset_bufarray.buf6._y:=0] - 269649 t.registers.read_write_demux._c_f_buf[0] : 0 [by t.registers.read_write_demux.c_buf_f.buf1._y:=1] - 271576 t.registers.atree[1].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 274158 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1] - 280228 t.registers._out_encoder[1] : 0 [by t.registers.atree[1].and2s[0]._y:=1] - 280309 t.registers.and_encoder[1]._y : 1 [by t.registers._out_encoder[1]:=0] - 286232 t.registers.ff_t[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 287887 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.registers.atree[2].in[1]:=0] - 287979 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1] - 290084 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.registers.ff_t[0].d:=0] - 291386 t.registers._clock_word_temp[1] : 0 [by t.registers.and_encoder[1]._y:=1] - 293130 t.registers.clock_buffer[1].buf1._y : 1 [by t.registers._clock_word_temp[1]:=0] - 293743 t.registers.ff_f[2].clk_B : 0 [by t.registers.clock_buffer[1].buf1._y:=1] - 293788 t.registers.ff_f[3]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0] - 294313 t.registers.ff_f[3].__clk_B : 0 [by t.registers.ff_f[3]._clk_B:=1] - 294740 t.registers.ff_t[2]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0] - 295392 t.registers.ff_t[3]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0] - 295444 t.registers.ff_t[3].__clk_B : 0 [by t.registers.ff_t[3]._clk_B:=1] - 295640 t.registers.ff_t[2].__clk_B : 0 [by t.registers.ff_t[2]._clk_B:=1] - 295778 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1] - 295785 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0] - 298395 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1] - 304215 t.registers.ff_t[1].__clk_B : 0 [by t.registers.ff_t[1]._clk_B:=1] - 304862 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0] - 304864 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1] - 307765 t.registers.ff_f[2]._clk_B : 1 [by t.registers.ff_f[2].clk_B:=0] - 308119 t.registers.ff_f[2].__clk_B : 0 [by t.registers.ff_f[2]._clk_B:=1] - 308501 t.registers._clock_word_temp[3] : 0 [by t.registers.and_encoder[3]._y:=1] - 308634 t.registers.clock_buffer[3].buf1._y : 1 [by t.registers._clock_word_temp[3]:=0] - 308635 t.registers.ff_f[6].clk_B : 0 [by t.registers.clock_buffer[3].buf1._y:=1] - 308636 t.registers.ff_t[7]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0] - 308639 t.registers.ff_f[6]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0] - 308718 t.registers.ff_f[6].__clk_B : 0 [by t.registers.ff_f[6]._clk_B:=1] - 309181 t.registers.ff_f[7]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0] - 311397 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1] - 311485 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[5]:=0] - 311614 t.registers.ff_f[7].__clk_B : 0 [by t.registers.ff_f[7]._clk_B:=1] - 319267 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1] - 319326 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0] - 319356 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1] - 321014 t.registers.ff_t[7].__clk_B : 0 [by t.registers.ff_t[7]._clk_B:=1] - 347594 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0] - 349061 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1] - 354198 t.registers.ff_t[6]._clk_B : 1 [by t.registers.ff_f[6].clk_B:=0] - 413702 t.registers.ff_t[6].__clk_B : 0 [by t.registers.ff_t[6]._clk_B:=1] -t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.clk_dly.and2[1]._y t.registers.clk_dly.dly[1].a t.registers.ff_val[1].y t.registers.clk_X.buf1._y t.registers._clock_temp t.registers.clk_dly.dly[1]._y t.registers.ff_val[1]._y t.registers.clk_dly.mu2[0]._s t.registers.clk_dly.dly[1].__y t.registers.clk_dly.mu2[0]._y t.dly_cfg[0] t.registers.clk_dly._a[1] t.registers.clk_dly.dly[2].__y t.registers.ff_val[0].y t.registers.clk_dly.dly[2].___y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.clk_dly.dly[1].y t.registers.clk_dly.dly[2].y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_val[1].a t.registers.clk_dly.mu2[1]._y t.registers.ff_val[0]._y +---------------------------------------------------------- +t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.clk_dly.and2[1]._y t.registers.clk_dly.dly[1].a t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.clk_X.buf1._y t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers.clk_dly.dly[1]._y t.registers.ff_val[1]._y t.registers.clk_dly.mu2[0]._s t.registers.clk_dly.dly[1].__y t.registers.clk_dly.mu2[0]._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.clk_dly._a[1] t.registers.clk_dly.dly[2].__y t.registers._in_write.a t.registers.ff_val[0].y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.clk_dly.dly[1].y t.registers.clk_dly.dly[2].y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_val[1].a t.registers.clk_dly.mu2[1]._y t.registers.ff_val[0]._y [1] reset completed - 413702 t.dly_cfg[0] : 1 - 413702 t.dly_cfg[1] : 1 - 414387 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1] - 433086 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1] - 449801 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0] - 449928 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1] - 450097 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0] - 450140 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1] - 450152 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0] - 451431 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1] - 451664 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0] - 451667 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1] - 451705 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0] - 451706 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1] - 464458 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0] - 464550 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1] - 467277 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0] - 467279 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1] - 467280 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0] - 468781 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1] - 468783 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0] +---------------------------------------------------------- [2] delay line set - 468783 t.registers.ff_t[0].d : 1 - 468783 t.registers.reading_activator_t[0].a : 1 - 468783 t.registers.atree[0].in[0] : 1 - 468783 t.registers.ff_t[1].d : 1 - 468783 t.registers.atree[0].in[1] : 1 - 468788 t.registers.read_write_demux.vc.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1] - 468791 t.registers.read_write_demux.vc.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1] - 468792 t.registers.read_write_demux.vc.ct.in[2] : 1 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=0] - 468801 t.registers.read_write_demux.vc.OR2_tf[0]._y : 0 [by t.registers.ff_t[0].d:=1] - 468837 t.registers.read_write_demux.vc.OR2_tf[1]._y : 0 [by t.registers.ff_t[1].d:=1] - 468838 t.registers.read_write_demux.vc.ct.in[1] : 1 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=0] - 468902 t.registers.read_write_demux.c_f_c_t_or._y : 0 [by t.registers.reading_activator_t[0].a:=1] - 468939 t.registers.read_write_demux.vc.ct.in[0] : 1 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=0] - 468966 t.registers.read_write_demux._c_v : 1 [by t.registers.read_write_demux.c_f_c_t_or._y:=0] - 469062 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 0 [by t.registers.read_write_demux.vc.ct.in[0]:=1] - 469064 t.registers.read_write_demux.vc.ct.tmp[4] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=0] - 469855 t.registers.read_write_demux.vc.ct.in[3] : 1 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=0] - 469892 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 0 [by t.registers.read_write_demux.vc.ct.in[3]:=1] - 470035 t.registers.read_write_demux.vc.ct.tmp[5] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=0] - 470086 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 0 [by t.registers.read_write_demux.vc.ct.tmp[5]:=1] - 470528 t.registers.read_write_demux._in_v : 1 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=0] - 470529 t.registers.read_write_demux.c_el._y : 0 [by t.registers.read_write_demux._in_v:=1] - 470538 t.registers.read_write_demux._in_c_v_ : 1 [by t.registers.read_write_demux.c_el._y:=0] - 470539 t.registers.read_write_demux.in_v_buf._y : 0 [by t.registers.read_write_demux._in_v:=1] - 470564 t.in.v : 1 [by t.registers.read_write_demux.in_v_buf._y:=0] - 474503 t.registers.read_write_demux.c_buf_t.buf1._y : 0 [by t.registers.reading_activator_t[0].a:=1] - 484756 t.registers.read_write_demux._c_t_buf[0] : 1 [by t.registers.read_write_demux.c_buf_t.buf1._y:=0] - 484901 t.registers.read_write_demux.out1_f_buf_func[3]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1] - 484986 t.registers.read_write_demux.out1_t_buf_func[1]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1] - 485000 t.registers._in_read_temp.d[1].t : 1 [by t.registers.read_write_demux.out1_t_buf_func[1]._y:=0] - 485592 t.registers._in_read_temp.d[3].f : 1 [by t.registers.read_write_demux.out1_f_buf_func[3]._y:=0] - 486543 t.registers.val_input_read.OR2_tf[1]._y : 0 [by t.registers._in_read_temp.d[1].t:=1] - 487203 t.registers.val_input_read.OR2_tf[3]._y : 0 [by t.registers._in_read_temp.d[3].f:=1] - 487214 t.registers.val_input_read.ct.in[3] : 1 [by t.registers.val_input_read.OR2_tf[3]._y:=0] - 488277 t.registers.read_write_demux.out1_f_buf_func[2]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1] - 488278 t.registers._in_read_temp.d[2].f : 1 [by t.registers.read_write_demux.out1_f_buf_func[2]._y:=0] - 488279 t.registers.val_input_read.OR2_tf[2]._y : 0 [by t.registers._in_read_temp.d[2].f:=1] - 494780 t.registers.val_input_read.ct.in[2] : 1 [by t.registers.val_input_read.OR2_tf[2]._y:=0] - 495419 t.registers.val_input_read.ct.C2Els[1]._y : 0 [by t.registers.val_input_read.ct.in[2]:=1] - 497212 t.registers.val_input_read.ct.tmp[5] : 1 [by t.registers.val_input_read.ct.C2Els[1]._y:=0] - 500924 t.registers.read_write_demux.out1_t_buf_func[0]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1] - 501056 t.registers._in_read_temp.d[0].t : 1 [by t.registers.read_write_demux.out1_t_buf_func[0]._y:=0] - 501057 t.registers.val_input_read.OR2_tf[0]._y : 0 [by t.registers._in_read_temp.d[0].t:=1] - 501074 t.registers.val_input_read.ct.in[0] : 1 [by t.registers.val_input_read.OR2_tf[0]._y:=0] - 504055 t.registers.val_input_read.ct.in[1] : 1 [by t.registers.val_input_read.OR2_tf[1]._y:=0] - 504207 t.registers.val_input_read.ct.C2Els[0]._y : 0 [by t.registers.val_input_read.ct.in[1]:=1] - 507190 t.registers.val_input_read.ct.tmp[4] : 1 [by t.registers.val_input_read.ct.C2Els[0]._y:=0] - 507193 t.registers.val_input_read.ct.C2Els[2]._y : 0 [by t.registers.val_input_read.ct.tmp[4]:=1] - 507617 t.registers._in_read.v : 1 [by t.registers.val_input_read.ct.C2Els[2]._y:=0] - 507623 t.registers.read_write_demux.out_or._y : 0 [by t.registers._in_read.v:=1] - 510211 t.registers.read_write_demux._out_v : 1 [by t.registers.read_write_demux.out_or._y:=0] - 512672 t.registers.read_write_demux.inack_ctl._y : 0 [by t.registers.read_write_demux._out_v:=1] - 513502 t.registers.ack_and.a : 1 [by t.registers.read_write_demux.inack_ctl._y:=0] - 519321 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1] - 519323 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0] - 519517 t.registers.and_encoder[0]._y : 0 [by t.registers._out_encoder[0]:=1] - 520120 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0] - 520258 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1] - 520275 t.registers.ff_f[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0] - 520276 t.registers.ff_t[0]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1] - 520276 t.registers.ff_t[1]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1] - 520277 t.registers.ff_t[1].__clk_B : 1 [by t.registers.ff_t[1]._clk_B:=0] - 520292 t.registers.ff_f[0]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1] - 520296 t.registers.ff_t[1]._mqib : 0 [by t.registers.ff_t[1].__clk_B:=1] - 520460 t.registers.ff_f[0].__clk_B : 1 [by t.registers.ff_f[0]._clk_B:=0] - 520701 t.registers.ff_f[1]._clk_B : 0 [by t.registers.ff_f[0].clk_B:=1] - 520835 t.registers.ff_t[1]._mqi : 1 [by t.registers.ff_t[1]._mqib:=0] - 520862 t.registers.ff_f[1].__clk_B : 1 [by t.registers.ff_f[1]._clk_B:=0] - 521302 t.registers.ff_t[0].__clk_B : 1 [by t.registers.ff_t[0]._clk_B:=0] - 521475 t.registers.ff_t[0]._mqib : 0 [by t.registers.ff_t[0].__clk_B:=1] - 524022 t.registers.ff_t[0]._mqi : 1 [by t.registers.ff_t[0]._mqib:=0] - 536434 t.registers.read_write_demux._en : 0 [by t.registers.ack_and.a:=1] - 536435 t.registers.read_write_demux.out1_en_buf_t.buf1._y : 1 [by t.registers.read_write_demux._en:=0] - 536435 t.registers.read_write_demux.out2_en_buf_t.buf1._y : 1 [by t.registers.read_write_demux._en:=0] - 536642 t.registers.read_write_demux._en1_X_t[0] : 0 [by t.registers.read_write_demux.out1_en_buf_t.buf1._y:=1] - 536824 t.registers.read_write_demux.out1_en_buf_f.buf1._y : 1 [by t.registers.read_write_demux._en:=0] - 536852 t.registers.read_write_demux._en1_X_f[0] : 0 [by t.registers.read_write_demux.out1_en_buf_f.buf1._y:=1] - 537268 t.registers.read_write_demux._en2_X_t[0] : 0 [by t.registers.read_write_demux.out2_en_buf_t.buf1._y:=1] - 551495 t.registers.read_write_demux.out2_en_buf_f.buf1._y : 1 [by t.registers.read_write_demux._en:=0] - 551502 t.registers.read_write_demux._en2_X_f[0] : 0 [by t.registers.read_write_demux.out2_en_buf_f.buf1._y:=1] -WRONG ASSERT: "t.registers._in_write.d.d[0].t" has value 0 and not 1. -WRONG ASSERT: "t.registers._in_write.d.d[1].t" has value 0 and not 1. -WRONG ASSERT: "t.registers._in_write.d.d[2].f" has value 0 and not 1. -WRONG ASSERT: "t.registers._in_write.d.d[3].f" has value 0 and not 1. -WRONG ASSERT: "t.registers._clock" has value 1 and not 0. - 551502 t.registers.ff_t[0].d : 0 - 551502 t.registers.reading_activator_t[0].a : 0 - 551502 t.registers.atree[0].in[0] : 0 - 551502 t.registers.ff_t[1].d : 0 - 551502 t.registers.atree[0].in[1] : 0 - 551506 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.registers.ff_t[0].d:=0] - 551645 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1] - 551668 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0] - 551916 t.registers.ff_t[0]._mqib : 1 [by t.registers.ff_t[0].d:=0] - 552111 t.registers.ff_t[0]._mqi : 0 [by t.registers.ff_t[0]._mqib:=1] - 552358 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0] - 552360 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1] - 552435 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.registers.ff_t[1].d:=0] - 553281 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.registers.reading_activator_t[0].a:=0] - 553287 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1] - 560147 t.registers.ff_t[1]._mqib : 1 [by t.registers.ff_t[1].d:=0] - 560401 t.registers.ff_t[1]._mqi : 0 [by t.registers.ff_t[1]._mqib:=1] - 574376 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.registers.reading_activator_t[0].a:=0] - 574384 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1] - 577877 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] - 577878 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0] - 577884 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] - 591372 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] - 594462 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1] - 594688 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0] - 595507 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1] - 605884 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1] - 605885 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[1]:=0] - 605891 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1] - 605893 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[4]:=0] - 609455 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1] - 609470 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0] - 609577 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1] - 628920 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] - 629013 t.registers.ff_f[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1] - 629771 t.registers.ff_t[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 630256 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0] - 630257 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1] - 630487 t.registers.ff_t[0].__clk_B : 0 [by t.registers.ff_t[0]._clk_B:=1] - 630665 t.registers.ff_f[0]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 631636 t.registers.ff_t[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 631637 t.registers.ff_t[1].__clk_B : 0 [by t.registers.ff_t[1]._clk_B:=1] - 632405 t.registers.ff_f[0].__clk_B : 0 [by t.registers.ff_f[0]._clk_B:=1] - 632952 t.registers.ff_f[1]._clk_B : 1 [by t.registers.ff_f[0].clk_B:=0] - 645104 t.registers.ff_f[1].__clk_B : 0 [by t.registers.ff_f[1]._clk_B:=1] -[3] clock checked -Node `t.registers.ff[0].q' not found -Node `t.registers.ff[1].q' not found +---------------------------------------------------------- +WARNING: weak-interference `t.registers._in_write_temp.d[0].t' +>> cause: t.registers.read_write_demux.out2_t_buf_func[0]._y (val: X) +>> time: 555402 +WARNING: weak-interference `t.registers._in_write_temp.d[1].t' +>> cause: t.registers.read_write_demux.out2_t_buf_func[1]._y (val: X) +>> time: 555410 +WARNING: weak-interference `t.registers._in_write_temp.d[2].f' +>> cause: t.registers.read_write_demux.out2_f_buf_func[2]._y (val: X) +>> time: 555426 +WARNING: weak-interference `t.registers.val_input_write.OR2_tf[1]._y' +>> cause: t.registers._in_write_temp.d[1].t (val: X) +>> time: 555555 +WARNING: weak-interference `t.registers.val_input_write.ct.in[1]' +>> cause: t.registers.val_input_write.OR2_tf[1]._y (val: X) +>> time: 555785 +WARNING: weak-interference `t.registers.val_input_write.OR2_tf[0]._y' +>> cause: t.registers._in_write_temp.d[0].t (val: X) +>> time: 558923 +WARNING: weak-interference `t.registers.val_input_write.ct.in[0]' +>> cause: t.registers.val_input_write.OR2_tf[0]._y (val: X) +>> time: 558937 +WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[0]._y' +>> cause: t.registers.val_input_write.ct.in[0] (val: X) +>> time: 560480 +WARNING: weak-interference `t.registers.val_input_write.ct.tmp[4]' +>> cause: t.registers.val_input_write.ct.C2Els[0]._y (val: X) +>> time: 562091 +WARNING: weak-interference `t.registers._in_write_temp.d[3].f' +>> cause: t.registers.read_write_demux.out2_f_buf_func[3]._y (val: X) +>> time: 565654 +WARNING: weak-interference `t.registers.val_input_write.OR2_tf[3]._y' +>> cause: t.registers._in_write_temp.d[3].f (val: X) +>> time: 565665 +WARNING: weak-interference `t.registers.val_input_write.ct.in[3]' +>> cause: t.registers.val_input_write.OR2_tf[3]._y (val: X) +>> time: 565666 +WARNING: weak-interference `t.registers.val_input_write.OR2_tf[2]._y' +>> cause: t.registers._in_write_temp.d[2].f (val: X) +>> time: 571594 +WARNING: weak-interference `t.registers.val_input_write.ct.in[2]' +>> cause: t.registers.val_input_write.OR2_tf[2]._y (val: X) +>> time: 578095 +WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[1]._y' +>> cause: t.registers.val_input_write.ct.in[2] (val: X) +>> time: 578734 +WARNING: weak-interference `t.registers.val_input_write.ct.tmp[5]' +>> cause: t.registers.val_input_write.ct.C2Els[1]._y (val: X) +>> time: 580527 +WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[2]._y' +>> cause: t.registers.val_input_write.ct.tmp[5] (val: X) +>> time: 580659 +WARNING: weak-interference `t.registers.clk_dly.in' +>> cause: t.registers.val_input_write.ct.C2Els[2]._y (val: X) +>> time: 580660 +WARNING: weak-interference `t.registers.clk_dly.and2[0]._y' +>> cause: t.registers.clk_dly.in (val: X) +>> time: 580677 +WARNING: weak-interference `t.registers.read_write_demux.out_or._y' +>> cause: t.registers.clk_dly.in (val: X) +>> time: 580677 +WARNING: weak-interference `t.registers.clk_dly.dly[0].a' +>> cause: t.registers.clk_dly.and2[0]._y (val: X) +>> time: 580829 +WARNING: weak-interference `t.registers.clk_dly.dly[0]._y' +>> cause: t.registers.clk_dly.dly[0].a (val: X) +>> time: 580832 +WARNING: weak-interference `t.registers.clk_dly.dly[0].__y' +>> cause: t.registers.clk_dly.dly[0]._y (val: X) +>> time: 581256 +WARNING: weak-interference `t.registers.clk_dly.dly[0].___y' +>> cause: t.registers.clk_dly.dly[0].__y (val: X) +>> time: 581262 +WARNING: weak-interference `t.registers.read_write_demux._out_v' +>> cause: t.registers.read_write_demux.out_or._y (val: X) +>> time: 583660 +WARNING: weak-interference `t.registers.clk_dly.dly[0].y' +>> cause: t.registers.clk_dly.dly[0].___y (val: X) +>> time: 583850 +WARNING: weak-interference `t.registers.clk_dly.mu2[0]._y' +>> cause: t.registers.clk_dly.dly[0].y (val: X) +>> time: 584680 +WARNING: weak-interference `t.registers.ack_and.a' +>> cause: t.registers.read_write_demux.inack_ctl._y (val: X) +>> time: 586123 +WARNING: weak-interference `t.registers.read_write_demux._en' +>> cause: t.registers.ack_and.a (val: X) +>> time: 586317 +WARNING: weak-interference `t.registers.read_write_demux.out2_en_buf_f.buf1._y' +>> cause: t.registers.read_write_demux._en (val: X) +>> time: 586920 +WARNING: weak-interference `t.registers.read_write_demux.out1_en_buf_t.buf1._y' +>> cause: t.registers.read_write_demux._en (val: X) +>> time: 586920 +WARNING: weak-interference `t.registers.read_write_demux.out2_en_buf_t.buf1._y' +>> cause: t.registers.read_write_demux._en (val: X) +>> time: 586920 +WARNING: weak-interference `t.registers.read_write_demux.out1_en_buf_f.buf1._y' +>> cause: t.registers.read_write_demux._en (val: X) +>> time: 586920 +WARNING: weak-interference `t.registers.read_write_demux._en1_X_t[0]' +>> cause: t.registers.read_write_demux.out1_en_buf_t.buf1._y (val: X) +>> time: 586937 +WARNING: weak-interference `t.registers.read_write_demux._en2_X_t[0]' +>> cause: t.registers.read_write_demux.out2_en_buf_t.buf1._y (val: X) +>> time: 586937 +WARNING: weak-interference `t.registers.read_write_demux._en2_X_f[0]' +>> cause: t.registers.read_write_demux.out2_en_buf_f.buf1._y (val: X) +>> time: 587058 +WARNING: weak-interference `t.registers.read_write_demux._en1_X_f[0]' +>> cause: t.registers.read_write_demux.out1_en_buf_f.buf1._y (val: X) +>> time: 587346 +WARNING: weak-interference `t.registers.clk_dly._a[1]' +>> cause: t.registers.clk_dly.mu2[0]._y (val: X) +>> time: 607612 +WARNING: weak-interference `t.registers.clk_dly.and2[1]._y' +>> cause: t.registers.clk_dly._a[1] (val: X) +>> time: 607619 +WARNING: weak-interference `t.registers.clk_dly.dly[1].a' +>> cause: t.registers.clk_dly.and2[1]._y (val: X) +>> time: 608033 +WARNING: weak-interference `t.registers.clk_dly.dly[1]._y' +>> cause: t.registers.clk_dly.dly[1].a (val: X) +>> time: 608037 +WARNING: weak-interference `t.registers.clk_dly.dly[1].__y' +>> cause: t.registers.clk_dly.dly[1]._y (val: X) +>> time: 609816 +WARNING: weak-interference `t.registers.clk_dly.dly[1].___y' +>> cause: t.registers.clk_dly.dly[1].__y (val: X) +>> time: 632690 +WARNING: weak-interference `t.registers.clk_dly.dly[1].y' +>> cause: t.registers.clk_dly.dly[1].___y (val: X) +>> time: 641335 +WARNING: weak-interference `t.registers.clk_dly.dly[2]._y' +>> cause: t.registers.clk_dly.dly[1].y (val: X) +>> time: 642268 +WARNING: weak-interference `t.registers.clk_dly.dly[2].__y' +>> cause: t.registers.clk_dly.dly[2]._y (val: X) +>> time: 643124 +WARNING: weak-interference `t.registers.clk_dly.dly[2].___y' +>> cause: t.registers.clk_dly.dly[2].__y (val: X) +>> time: 643263 +WARNING: weak-interference `t.registers.clk_dly.dly[2].y' +>> cause: t.registers.clk_dly.dly[2].___y (val: X) +>> time: 669472 +WARNING: weak-interference `t.registers.clk_dly.mu2[1]._y' +>> cause: t.registers.clk_dly.dly[2].y (val: X) +>> time: 669474 +WARNING: weak-interference `t.registers._clock_temp' +>> cause: t.registers.clk_dly.mu2[1]._y (val: X) +>> time: 722923 +WARNING: weak-interference `t.registers._clock_temp_inv' +>> cause: t.registers._clock_temp (val: X) +>> time: 722929 +WARNING: weak-interference `t.registers.clk_X.buf1._y' +>> cause: t.registers._clock_temp_inv (val: X) +>> time: 723183 +WARNING: weak-interference `t.registers._clock' +>> cause: t.registers.clk_X.buf1._y (val: X) +>> time: 723191 +WARNING: weak-interference `t.registers.and_encoder[0]._y' +>> cause: t.registers._clock (val: X) +>> time: 723192 +WARNING: weak-interference `t.registers._clock_word_temp[0]' +>> cause: t.registers.and_encoder[0]._y (val: X) +>> time: 723198 +WARNING: weak-interference `t.registers.clock_buffer[0].buf1._y' +>> cause: t.registers._clock_word_temp[0] (val: X) +>> time: 774234 +WARNING: weak-interference `t.registers.ff_f[0].clk_B' +>> cause: t.registers.clock_buffer[0].buf1._y (val: X) +>> time: 777324 +WARNING: weak-interference `t.registers.ff_f[0]._clk_B' +>> cause: t.registers.ff_f[0].clk_B (val: X) +>> time: 777550 +WARNING: weak-interference `t.registers.ff_f[1]._clk_B' +>> cause: t.registers.ff_f[0].clk_B (val: X) +>> time: 777550 +WARNING: weak-interference `t.registers.ff_t[0]._clk_B' +>> cause: t.registers.ff_f[0].clk_B (val: X) +>> time: 777550 +WARNING: weak-interference `t.registers.ff_t[1]._clk_B' +>> cause: t.registers.ff_f[0].clk_B (val: X) +>> time: 777550 +WARNING: weak-interference `t.registers.ff_f[1].__clk_B' +>> cause: t.registers.ff_f[1]._clk_B (val: X) +>> time: 777551 +WARNING: weak-interference `t.registers.ff_t[1].__clk_B' +>> cause: t.registers.ff_t[1]._clk_B (val: X) +>> time: 777552 +WARNING: weak-interference `t.registers.ff_t[1]._sqib' +>> cause: t.registers.ff_t[1]._clk_B (val: X) +>> time: 777552 +WARNING: weak-interference `t.registers.ff_t[0].__clk_B' +>> cause: t.registers.ff_t[0]._clk_B (val: X) +>> time: 777556 +WARNING: weak-interference `t.registers.ff_t[0]._sqib' +>> cause: t.registers.ff_t[0]._clk_B (val: X) +>> time: 777556 +WARNING: weak-interference `t.registers.ff_t[0]._sqi' +>> cause: t.registers.ff_t[0]._sqib (val: X) +>> time: 777649 +WARNING: weak-interference `t.data[0].d[0]' +>> cause: t.registers.ff_t[0]._sqib (val: X) +>> time: 777649 +WARNING: weak-interference `t.registers.ff_f[0].__clk_B' +>> cause: t.registers.ff_f[0]._clk_B (val: X) +>> time: 778369 +WARNING: weak-interference `t.registers.ff_t[1]._sqi' +>> cause: t.registers.ff_t[1]._sqib (val: X) +>> time: 798353 +WARNING: weak-interference `t.data[0].d[1]' +>> cause: t.registers.ff_t[1]._sqib (val: X) +>> time: 798353 +WRONG ASSERT: "t.registers._in_write.d.d[0].t" has value X and not 1. +WRONG ASSERT: "t.registers._in_write.d.d[1].t" has value X and not 1. +WRONG ASSERT: "t.registers._in_write.d.d[2].f" has value X and not 1. +WRONG ASSERT: "t.registers._in_write.d.d[3].f" has value X and not 1. +WRONG ASSERT: "t.registers._clock" has value X and not 0. +WARNING: weak-interference `t.registers.ff_t[0]._mqib' +>> cause: t.registers.ff_t[0].d (val: 0) +>> time: 800976 +WARNING: weak-interference `t.registers.ff_t[1]._mqib' +>> cause: t.registers.ff_t[1].d (val: 0) +>> time: 800976 +WARNING: weak-interference `t.registers.ff_t[0]._mqi' +>> cause: t.registers.ff_t[0]._mqib (val: X) +>> time: 800977 +WARNING: weak-interference `t.registers.ff_t[1]._mqi' +>> cause: t.registers.ff_t[1]._mqib (val: X) +>> time: 800982 +WRONG ASSERT: "t.registers._clock" has value X and not 1. +WRONG ASSERT: "t.registers.ff_t[0].q" has value X and not 1. +WRONG ASSERT: "t.registers.ff_t[1].q" has value X and not 1. +[3] first writing done +---------------------------------------------------------- diff --git a/test/unit_tests/register_wrw/run/test.prs b/test/unit_tests/register_wrw/run/test.prs index 7d56834..853de2c 100644 --- a/test/unit_tests/register_wrw/run/test.prs +++ b/test/unit_tests/register_wrw/run/test.prs @@ -54,13 +54,12 @@ = "t.registers._in_flag.d.d[0].t" "t.registers.read_write_demux.cond.d.d[0].t" = "t.registers._in_flag.d.d[0].d[0]" "t.registers.read_write_demux.cond.d.d[0].d[0]" = "t.registers._in_flag.d.d[0].d[1]" "t.registers.read_write_demux.cond.d.d[0].d[1]" -"t.registers.ack_and.a"&"t.registers.ack_and.b"&"t.registers.ack_and.c"->"t.registers.ack_and._y"- -~("t.registers.ack_and.a"&"t.registers.ack_and.b"&"t.registers.ack_and.c")->"t.registers.ack_and._y"+ +"t.registers.ack_and.a"&"t.registers.ack_and.b"->"t.registers.ack_and._y"- +~("t.registers.ack_and.a"&"t.registers.ack_and.b")->"t.registers.ack_and._y"+ "t.registers.ack_and._y"->"t.registers.ack_and.y"- ~("t.registers.ack_and._y")->"t.registers.ack_and.y"+ -= "t.registers.ack_and.b" "t.registers._in_flag.a" -= "t.registers.ack_and.b" "t.registers.ack_and.a" -= "t.registers.ack_and.b" "t.registers._in_temp2.a" += "t.registers.ack_and.a" "t.registers._in_temp2.a" += "t.registers.ack_and.a" "t.registers._in_flag.a" = "t.registers._out_temp.d[0].d[0]" "t.registers._out_temp.d[0].f" = "t.registers._out_temp.d[0].d[1]" "t.registers._out_temp.d[0].t" = "t.registers._out_temp.d[1].d[0]" "t.registers._out_temp.d[1].f" @@ -542,22 +541,22 @@ = "t.registers._in_write_temp.d[1].d[1]" "t.registers._in_write_temp.d[1].t" = "t.registers._in_write_temp.d[0].d[0]" "t.registers._in_write_temp.d[0].f" = "t.registers._in_write_temp.d[0].d[1]" "t.registers._in_write_temp.d[0].t" -= "t.registers._in_write_temp.d[0].f" "t.registers.val_input.in.d[0].f" -= "t.registers._in_write_temp.d[0].t" "t.registers.val_input.in.d[0].t" -= "t.registers._in_write_temp.d[0].d[0]" "t.registers.val_input.in.d[0].d[0]" -= "t.registers._in_write_temp.d[0].d[1]" "t.registers.val_input.in.d[0].d[1]" -= "t.registers._in_write_temp.d[1].f" "t.registers.val_input.in.d[1].f" -= "t.registers._in_write_temp.d[1].t" "t.registers.val_input.in.d[1].t" -= "t.registers._in_write_temp.d[1].d[0]" "t.registers.val_input.in.d[1].d[0]" -= "t.registers._in_write_temp.d[1].d[1]" "t.registers.val_input.in.d[1].d[1]" -= "t.registers._in_write_temp.d[2].f" "t.registers.val_input.in.d[2].f" -= "t.registers._in_write_temp.d[2].t" "t.registers.val_input.in.d[2].t" -= "t.registers._in_write_temp.d[2].d[0]" "t.registers.val_input.in.d[2].d[0]" -= "t.registers._in_write_temp.d[2].d[1]" "t.registers.val_input.in.d[2].d[1]" -= "t.registers._in_write_temp.d[3].f" "t.registers.val_input.in.d[3].f" -= "t.registers._in_write_temp.d[3].t" "t.registers.val_input.in.d[3].t" -= "t.registers._in_write_temp.d[3].d[0]" "t.registers.val_input.in.d[3].d[0]" -= "t.registers._in_write_temp.d[3].d[1]" "t.registers.val_input.in.d[3].d[1]" += "t.registers._in_write_temp.d[0].f" "t.registers.val_input_write.in.d[0].f" += "t.registers._in_write_temp.d[0].t" "t.registers.val_input_write.in.d[0].t" += "t.registers._in_write_temp.d[0].d[0]" "t.registers.val_input_write.in.d[0].d[0]" += "t.registers._in_write_temp.d[0].d[1]" "t.registers.val_input_write.in.d[0].d[1]" += "t.registers._in_write_temp.d[1].f" "t.registers.val_input_write.in.d[1].f" += "t.registers._in_write_temp.d[1].t" "t.registers.val_input_write.in.d[1].t" += "t.registers._in_write_temp.d[1].d[0]" "t.registers.val_input_write.in.d[1].d[0]" += "t.registers._in_write_temp.d[1].d[1]" "t.registers.val_input_write.in.d[1].d[1]" += "t.registers._in_write_temp.d[2].f" "t.registers.val_input_write.in.d[2].f" += "t.registers._in_write_temp.d[2].t" "t.registers.val_input_write.in.d[2].t" += "t.registers._in_write_temp.d[2].d[0]" "t.registers.val_input_write.in.d[2].d[0]" += "t.registers._in_write_temp.d[2].d[1]" "t.registers.val_input_write.in.d[2].d[1]" += "t.registers._in_write_temp.d[3].f" "t.registers.val_input_write.in.d[3].f" += "t.registers._in_write_temp.d[3].t" "t.registers.val_input_write.in.d[3].t" += "t.registers._in_write_temp.d[3].d[0]" "t.registers.val_input_write.in.d[3].d[0]" += "t.registers._in_write_temp.d[3].d[1]" "t.registers.val_input_write.in.d[3].d[1]" = "t.registers._in_write_temp.d[0].f" "t.registers._in_write.d.d[0].f" = "t.registers._in_write_temp.d[0].t" "t.registers._in_write.d.d[0].t" = "t.registers._in_write_temp.d[0].d[0]" "t.registers._in_write.d.d[0].d[0]" @@ -582,6 +581,101 @@ = "t.registers._in_write_temp.d[1].d[1]" "t.registers._in_write_temp.d[1].t" = "t.registers._in_write_temp.d[0].d[0]" "t.registers._in_write_temp.d[0].f" = "t.registers._in_write_temp.d[0].d[1]" "t.registers._in_write_temp.d[0].t" +~"t.registers.val_input_write.ct.C2Els[0].c1"&~"t.registers.val_input_write.ct.C2Els[0].c2"->"t.registers.val_input_write.ct.C2Els[0]._y"+ +"t.registers.val_input_write.ct.C2Els[0].c1"&"t.registers.val_input_write.ct.C2Els[0].c2"->"t.registers.val_input_write.ct.C2Els[0]._y"- +"t.registers.val_input_write.ct.C2Els[0]._y"->"t.registers.val_input_write.ct.C2Els[0].y"- +~("t.registers.val_input_write.ct.C2Els[0]._y")->"t.registers.val_input_write.ct.C2Els[0].y"+ +~"t.registers.val_input_write.ct.C2Els[1].c1"&~"t.registers.val_input_write.ct.C2Els[1].c2"->"t.registers.val_input_write.ct.C2Els[1]._y"+ +"t.registers.val_input_write.ct.C2Els[1].c1"&"t.registers.val_input_write.ct.C2Els[1].c2"->"t.registers.val_input_write.ct.C2Els[1]._y"- +"t.registers.val_input_write.ct.C2Els[1]._y"->"t.registers.val_input_write.ct.C2Els[1].y"- +~("t.registers.val_input_write.ct.C2Els[1]._y")->"t.registers.val_input_write.ct.C2Els[1].y"+ +~"t.registers.val_input_write.ct.C2Els[2].c1"&~"t.registers.val_input_write.ct.C2Els[2].c2"->"t.registers.val_input_write.ct.C2Els[2]._y"+ +"t.registers.val_input_write.ct.C2Els[2].c1"&"t.registers.val_input_write.ct.C2Els[2].c2"->"t.registers.val_input_write.ct.C2Els[2]._y"- +"t.registers.val_input_write.ct.C2Els[2]._y"->"t.registers.val_input_write.ct.C2Els[2].y"- +~("t.registers.val_input_write.ct.C2Els[2]._y")->"t.registers.val_input_write.ct.C2Els[2].y"+ += "t.registers.val_input_write.ct.tmp[4]" "t.registers.val_input_write.ct.C2Els[2].c1" += "t.registers.val_input_write.ct.tmp[4]" "t.registers.val_input_write.ct.C2Els[0].y" += "t.registers.val_input_write.ct.tmp[5]" "t.registers.val_input_write.ct.C2Els[2].c2" += "t.registers.val_input_write.ct.tmp[5]" "t.registers.val_input_write.ct.C2Els[1].y" += "t.registers.val_input_write.ct.supply.vdd" "t.registers.val_input_write.ct.C2Els[2].vdd" += "t.registers.val_input_write.ct.supply.vdd" "t.registers.val_input_write.ct.C2Els[1].vdd" += "t.registers.val_input_write.ct.supply.vdd" "t.registers.val_input_write.ct.C2Els[0].vdd" += "t.registers.val_input_write.ct.supply.vss" "t.registers.val_input_write.ct.C2Els[2].vss" += "t.registers.val_input_write.ct.supply.vss" "t.registers.val_input_write.ct.C2Els[1].vss" += "t.registers.val_input_write.ct.supply.vss" "t.registers.val_input_write.ct.C2Els[0].vss" += "t.registers.val_input_write.ct.in[0]" "t.registers.val_input_write.ct.C2Els[0].c1" += "t.registers.val_input_write.ct.in[0]" "t.registers.val_input_write.ct.tmp[0]" += "t.registers.val_input_write.ct.in[1]" "t.registers.val_input_write.ct.C2Els[0].c2" += "t.registers.val_input_write.ct.in[1]" "t.registers.val_input_write.ct.tmp[1]" += "t.registers.val_input_write.ct.in[2]" "t.registers.val_input_write.ct.C2Els[1].c1" += "t.registers.val_input_write.ct.in[2]" "t.registers.val_input_write.ct.tmp[2]" += "t.registers.val_input_write.ct.in[3]" "t.registers.val_input_write.ct.C2Els[1].c2" += "t.registers.val_input_write.ct.in[3]" "t.registers.val_input_write.ct.tmp[3]" += "t.registers.val_input_write.ct.out" "t.registers.val_input_write.ct.C2Els[2].y" += "t.registers.val_input_write.ct.out" "t.registers.val_input_write.ct.tmp[6]" += "t.registers.val_input_write.ct.in[0]" "t.registers.val_input_write.OR2_tf[0].y" += "t.registers.val_input_write.ct.in[1]" "t.registers.val_input_write.OR2_tf[1].y" += "t.registers.val_input_write.ct.in[2]" "t.registers.val_input_write.OR2_tf[2].y" += "t.registers.val_input_write.ct.in[3]" "t.registers.val_input_write.OR2_tf[3].y" +"t.registers.val_input_write.OR2_tf[0].a"|"t.registers.val_input_write.OR2_tf[0].b"->"t.registers.val_input_write.OR2_tf[0]._y"- +~("t.registers.val_input_write.OR2_tf[0].a"|"t.registers.val_input_write.OR2_tf[0].b")->"t.registers.val_input_write.OR2_tf[0]._y"+ +"t.registers.val_input_write.OR2_tf[0]._y"->"t.registers.val_input_write.OR2_tf[0].y"- +~("t.registers.val_input_write.OR2_tf[0]._y")->"t.registers.val_input_write.OR2_tf[0].y"+ +"t.registers.val_input_write.OR2_tf[1].a"|"t.registers.val_input_write.OR2_tf[1].b"->"t.registers.val_input_write.OR2_tf[1]._y"- +~("t.registers.val_input_write.OR2_tf[1].a"|"t.registers.val_input_write.OR2_tf[1].b")->"t.registers.val_input_write.OR2_tf[1]._y"+ +"t.registers.val_input_write.OR2_tf[1]._y"->"t.registers.val_input_write.OR2_tf[1].y"- +~("t.registers.val_input_write.OR2_tf[1]._y")->"t.registers.val_input_write.OR2_tf[1].y"+ +"t.registers.val_input_write.OR2_tf[2].a"|"t.registers.val_input_write.OR2_tf[2].b"->"t.registers.val_input_write.OR2_tf[2]._y"- +~("t.registers.val_input_write.OR2_tf[2].a"|"t.registers.val_input_write.OR2_tf[2].b")->"t.registers.val_input_write.OR2_tf[2]._y"+ +"t.registers.val_input_write.OR2_tf[2]._y"->"t.registers.val_input_write.OR2_tf[2].y"- +~("t.registers.val_input_write.OR2_tf[2]._y")->"t.registers.val_input_write.OR2_tf[2].y"+ +"t.registers.val_input_write.OR2_tf[3].a"|"t.registers.val_input_write.OR2_tf[3].b"->"t.registers.val_input_write.OR2_tf[3]._y"- +~("t.registers.val_input_write.OR2_tf[3].a"|"t.registers.val_input_write.OR2_tf[3].b")->"t.registers.val_input_write.OR2_tf[3]._y"+ +"t.registers.val_input_write.OR2_tf[3]._y"->"t.registers.val_input_write.OR2_tf[3].y"- +~("t.registers.val_input_write.OR2_tf[3]._y")->"t.registers.val_input_write.OR2_tf[3].y"+ += "t.registers.val_input_write.supply.vss" "t.registers.val_input_write.ct.supply.vss" += "t.registers.val_input_write.supply.vdd" "t.registers.val_input_write.ct.supply.vdd" += "t.registers.val_input_write.supply.vdd" "t.registers.val_input_write.OR2_tf[3].vdd" += "t.registers.val_input_write.supply.vdd" "t.registers.val_input_write.OR2_tf[2].vdd" += "t.registers.val_input_write.supply.vdd" "t.registers.val_input_write.OR2_tf[1].vdd" += "t.registers.val_input_write.supply.vdd" "t.registers.val_input_write.OR2_tf[0].vdd" += "t.registers.val_input_write.supply.vss" "t.registers.val_input_write.OR2_tf[3].vss" += "t.registers.val_input_write.supply.vss" "t.registers.val_input_write.OR2_tf[2].vss" += "t.registers.val_input_write.supply.vss" "t.registers.val_input_write.OR2_tf[1].vss" += "t.registers.val_input_write.supply.vss" "t.registers.val_input_write.OR2_tf[0].vss" += "t.registers.val_input_write.out" "t.registers.val_input_write.ct.out" += "t.registers.val_input_write.in.d[0].d[0]" "t.registers.val_input_write.in.d[0].f" += "t.registers.val_input_write.in.d[0].d[1]" "t.registers.val_input_write.in.d[0].t" += "t.registers.val_input_write.in.d[1].d[0]" "t.registers.val_input_write.in.d[1].f" += "t.registers.val_input_write.in.d[1].d[1]" "t.registers.val_input_write.in.d[1].t" += "t.registers.val_input_write.in.d[2].d[0]" "t.registers.val_input_write.in.d[2].f" += "t.registers.val_input_write.in.d[2].d[1]" "t.registers.val_input_write.in.d[2].t" += "t.registers.val_input_write.in.d[3].d[0]" "t.registers.val_input_write.in.d[3].f" += "t.registers.val_input_write.in.d[3].d[1]" "t.registers.val_input_write.in.d[3].t" += "t.registers.val_input_write.in.d[3].d[0]" "t.registers.val_input_write.in.d[3].f" += "t.registers.val_input_write.in.d[3].d[1]" "t.registers.val_input_write.in.d[3].t" += "t.registers.val_input_write.in.d[2].d[0]" "t.registers.val_input_write.in.d[2].f" += "t.registers.val_input_write.in.d[2].d[1]" "t.registers.val_input_write.in.d[2].t" += "t.registers.val_input_write.in.d[1].d[0]" "t.registers.val_input_write.in.d[1].f" += "t.registers.val_input_write.in.d[1].d[1]" "t.registers.val_input_write.in.d[1].t" += "t.registers.val_input_write.in.d[0].d[0]" "t.registers.val_input_write.in.d[0].f" += "t.registers.val_input_write.in.d[0].d[1]" "t.registers.val_input_write.in.d[0].t" += "t.registers.val_input_write.in.d[3].d[0]" "t.registers.val_input_write.OR2_tf[3].b" += "t.registers.val_input_write.in.d[3].d[0]" "t.registers.val_input_write.in.d[3].f" += "t.registers.val_input_write.in.d[3].d[1]" "t.registers.val_input_write.OR2_tf[3].a" += "t.registers.val_input_write.in.d[3].d[1]" "t.registers.val_input_write.in.d[3].t" += "t.registers.val_input_write.in.d[2].d[0]" "t.registers.val_input_write.OR2_tf[2].b" += "t.registers.val_input_write.in.d[2].d[0]" "t.registers.val_input_write.in.d[2].f" += "t.registers.val_input_write.in.d[2].d[1]" "t.registers.val_input_write.OR2_tf[2].a" += "t.registers.val_input_write.in.d[2].d[1]" "t.registers.val_input_write.in.d[2].t" += "t.registers.val_input_write.in.d[1].d[0]" "t.registers.val_input_write.OR2_tf[1].b" += "t.registers.val_input_write.in.d[1].d[0]" "t.registers.val_input_write.in.d[1].f" += "t.registers.val_input_write.in.d[1].d[1]" "t.registers.val_input_write.OR2_tf[1].a" += "t.registers.val_input_write.in.d[1].d[1]" "t.registers.val_input_write.in.d[1].t" += "t.registers.val_input_write.in.d[0].d[0]" "t.registers.val_input_write.OR2_tf[0].b" += "t.registers.val_input_write.in.d[0].d[0]" "t.registers.val_input_write.in.d[0].f" += "t.registers.val_input_write.in.d[0].d[1]" "t.registers.val_input_write.OR2_tf[0].a" += "t.registers.val_input_write.in.d[0].d[1]" "t.registers.val_input_write.in.d[0].t" = "t.registers.reset_B" "t.registers.reset_buf_BX.a" = "t.registers.reset_B" "t.registers.read_write_demux.reset_B" = "t.registers._in_write.d.d[0].d[0]" "t.registers._in_write.d.d[0].f" @@ -836,8 +930,9 @@ ~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+ = "t.registers._reset_mem_BX" "t.registers.reset_bufarray.in" = "t.registers._reset_mem_BX" "t.registers.reset_buf_BXX.y" += "t.registers._ff_v" "t.registers._in_read.a" = "t.registers._ff_v" "t.registers.ff_validator.out" -= "t.registers._ff_v" "t.registers.ack_and.c" += "t.registers._ff_v" "t.registers.ack_and.b" = "t.registers.dly_cfg[0]" "t.registers.clk_dly.s[0]" = "t.registers.dly_cfg[1]" "t.registers.clk_dly.s[1]" = "t.registers.supply.vss" "t.registers.clock_buffer[3].supply.vss" @@ -866,8 +961,8 @@ = "t.registers.supply.vdd" "t.registers.clk_X.supply.vdd" = "t.registers.supply.vss" "t.registers.clk_dly.supply.vss" = "t.registers.supply.vdd" "t.registers.clk_dly.supply.vdd" -= "t.registers.supply.vss" "t.registers.val_input.supply.vss" -= "t.registers.supply.vdd" "t.registers.val_input.supply.vdd" += "t.registers.supply.vss" "t.registers.val_input_write.supply.vss" += "t.registers.supply.vdd" "t.registers.val_input_write.supply.vdd" = "t.registers.supply.vss" "t.registers.read_write_demux.supply.vss" = "t.registers.supply.vdd" "t.registers.read_write_demux.supply.vdd" = "t.registers.supply.vdd" "t.registers.reading_activator_f[7].vdd" @@ -1162,101 +1257,6 @@ ~("t.registers.reset_buf_BXX.a")->"t.registers.reset_buf_BXX._y"+ "t.registers.reset_buf_BXX._y"->"t.registers.reset_buf_BXX.y"- ~("t.registers.reset_buf_BXX._y")->"t.registers.reset_buf_BXX.y"+ -~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+ -"t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"- -"t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"- -~("t.registers.val_input.ct.C2Els[0]._y")->"t.registers.val_input.ct.C2Els[0].y"+ -~"t.registers.val_input.ct.C2Els[1].c1"&~"t.registers.val_input.ct.C2Els[1].c2"->"t.registers.val_input.ct.C2Els[1]._y"+ -"t.registers.val_input.ct.C2Els[1].c1"&"t.registers.val_input.ct.C2Els[1].c2"->"t.registers.val_input.ct.C2Els[1]._y"- -"t.registers.val_input.ct.C2Els[1]._y"->"t.registers.val_input.ct.C2Els[1].y"- -~("t.registers.val_input.ct.C2Els[1]._y")->"t.registers.val_input.ct.C2Els[1].y"+ -~"t.registers.val_input.ct.C2Els[2].c1"&~"t.registers.val_input.ct.C2Els[2].c2"->"t.registers.val_input.ct.C2Els[2]._y"+ -"t.registers.val_input.ct.C2Els[2].c1"&"t.registers.val_input.ct.C2Els[2].c2"->"t.registers.val_input.ct.C2Els[2]._y"- -"t.registers.val_input.ct.C2Els[2]._y"->"t.registers.val_input.ct.C2Els[2].y"- -~("t.registers.val_input.ct.C2Els[2]._y")->"t.registers.val_input.ct.C2Els[2].y"+ -= "t.registers.val_input.ct.tmp[4]" "t.registers.val_input.ct.C2Els[2].c1" -= "t.registers.val_input.ct.tmp[4]" "t.registers.val_input.ct.C2Els[0].y" -= "t.registers.val_input.ct.tmp[5]" "t.registers.val_input.ct.C2Els[2].c2" -= "t.registers.val_input.ct.tmp[5]" "t.registers.val_input.ct.C2Els[1].y" -= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C2Els[2].vdd" -= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C2Els[1].vdd" -= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C2Els[0].vdd" -= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C2Els[2].vss" -= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C2Els[1].vss" -= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C2Els[0].vss" -= "t.registers.val_input.ct.in[0]" "t.registers.val_input.ct.C2Els[0].c1" -= "t.registers.val_input.ct.in[0]" "t.registers.val_input.ct.tmp[0]" -= "t.registers.val_input.ct.in[1]" "t.registers.val_input.ct.C2Els[0].c2" -= "t.registers.val_input.ct.in[1]" "t.registers.val_input.ct.tmp[1]" -= "t.registers.val_input.ct.in[2]" "t.registers.val_input.ct.C2Els[1].c1" -= "t.registers.val_input.ct.in[2]" "t.registers.val_input.ct.tmp[2]" -= "t.registers.val_input.ct.in[3]" "t.registers.val_input.ct.C2Els[1].c2" -= "t.registers.val_input.ct.in[3]" "t.registers.val_input.ct.tmp[3]" -= "t.registers.val_input.ct.out" "t.registers.val_input.ct.C2Els[2].y" -= "t.registers.val_input.ct.out" "t.registers.val_input.ct.tmp[6]" -= "t.registers.val_input.ct.in[0]" "t.registers.val_input.OR2_tf[0].y" -= "t.registers.val_input.ct.in[1]" "t.registers.val_input.OR2_tf[1].y" -= "t.registers.val_input.ct.in[2]" "t.registers.val_input.OR2_tf[2].y" -= "t.registers.val_input.ct.in[3]" "t.registers.val_input.OR2_tf[3].y" -"t.registers.val_input.OR2_tf[0].a"|"t.registers.val_input.OR2_tf[0].b"->"t.registers.val_input.OR2_tf[0]._y"- -~("t.registers.val_input.OR2_tf[0].a"|"t.registers.val_input.OR2_tf[0].b")->"t.registers.val_input.OR2_tf[0]._y"+ -"t.registers.val_input.OR2_tf[0]._y"->"t.registers.val_input.OR2_tf[0].y"- -~("t.registers.val_input.OR2_tf[0]._y")->"t.registers.val_input.OR2_tf[0].y"+ -"t.registers.val_input.OR2_tf[1].a"|"t.registers.val_input.OR2_tf[1].b"->"t.registers.val_input.OR2_tf[1]._y"- -~("t.registers.val_input.OR2_tf[1].a"|"t.registers.val_input.OR2_tf[1].b")->"t.registers.val_input.OR2_tf[1]._y"+ -"t.registers.val_input.OR2_tf[1]._y"->"t.registers.val_input.OR2_tf[1].y"- -~("t.registers.val_input.OR2_tf[1]._y")->"t.registers.val_input.OR2_tf[1].y"+ -"t.registers.val_input.OR2_tf[2].a"|"t.registers.val_input.OR2_tf[2].b"->"t.registers.val_input.OR2_tf[2]._y"- -~("t.registers.val_input.OR2_tf[2].a"|"t.registers.val_input.OR2_tf[2].b")->"t.registers.val_input.OR2_tf[2]._y"+ -"t.registers.val_input.OR2_tf[2]._y"->"t.registers.val_input.OR2_tf[2].y"- -~("t.registers.val_input.OR2_tf[2]._y")->"t.registers.val_input.OR2_tf[2].y"+ -"t.registers.val_input.OR2_tf[3].a"|"t.registers.val_input.OR2_tf[3].b"->"t.registers.val_input.OR2_tf[3]._y"- -~("t.registers.val_input.OR2_tf[3].a"|"t.registers.val_input.OR2_tf[3].b")->"t.registers.val_input.OR2_tf[3]._y"+ -"t.registers.val_input.OR2_tf[3]._y"->"t.registers.val_input.OR2_tf[3].y"- -~("t.registers.val_input.OR2_tf[3]._y")->"t.registers.val_input.OR2_tf[3].y"+ -= "t.registers.val_input.supply.vss" "t.registers.val_input.ct.supply.vss" -= "t.registers.val_input.supply.vdd" "t.registers.val_input.ct.supply.vdd" -= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[3].vdd" -= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[2].vdd" -= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[1].vdd" -= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[0].vdd" -= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[3].vss" -= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[2].vss" -= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[1].vss" -= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[0].vss" -= "t.registers.val_input.out" "t.registers.val_input.ct.out" -= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f" -= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t" -= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f" -= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t" -= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f" -= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t" -= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f" -= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t" -= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f" -= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t" -= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f" -= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t" -= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f" -= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t" -= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f" -= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t" -= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.OR2_tf[3].b" -= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f" -= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.OR2_tf[3].a" -= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t" -= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.OR2_tf[2].b" -= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f" -= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.OR2_tf[2].a" -= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t" -= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.OR2_tf[1].b" -= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f" -= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.OR2_tf[1].a" -= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t" -= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.OR2_tf[0].b" -= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f" -= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.OR2_tf[0].a" -= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t" "t.registers.clk_dly.and2[0].a"&"t.registers.clk_dly.and2[0].b"->"t.registers.clk_dly.and2[0]._y"- ~("t.registers.clk_dly.and2[0].a"&"t.registers.clk_dly.and2[0].b")->"t.registers.clk_dly.and2[0]._y"+ "t.registers.clk_dly.and2[0]._y"->"t.registers.clk_dly.and2[0].y"- @@ -1332,7 +1332,7 @@ = "t.registers.clk_dly.in" "t.registers.clk_dly.mu2[0].a" = "t.registers.clk_dly.in" "t.registers.clk_dly.and2[0].a" = "t.registers.clk_dly.in" "t.registers.clk_dly._a[0]" -= "t.registers.clk_dly.in" "t.registers.val_input.out" += "t.registers.clk_dly.in" "t.registers.val_input_write.out" = "t.registers.clk_dly.in" "t.registers._in_write.v" "t.registers.ff_val[0].a"|"t.registers.ff_val[0].b"->"t.registers.ff_val[0]._y"- ~("t.registers.ff_val[0].a"|"t.registers.ff_val[0].b")->"t.registers.ff_val[0]._y"+ diff --git a/test/unit_tests/register_wrw/test.prsim b/test/unit_tests/register_wrw/test.prsim index 0d2e2b5..3b7db2b 100644 --- a/test/unit_tests/register_wrw/test.prsim +++ b/test/unit_tests/register_wrw/test.prsim @@ -1,18 +1,13 @@ -watchall +#watchall system "echo '[0] start test'" +system "echo '----------------------------------------------------------'" set-qdi-channel-neutral "t.in" 5 -set-qdi-channel-neutral "t._in_write" 5 -set-qdi-channel-neutral "t._in_read" 5 set t.data[0].d[0] 0 set t.data[0].d[1] 0 set t.data[1].d[0] 0 set t.data[1].d[1] 0 -set t.registers._in_write.a 0 -set t.registers._in_read.a 0 -set t.registers._in_write.v 0 -set t.registers._in_read.v 0 - +set t.out.a 0 set Reset 0 cycle status X @@ -24,13 +19,16 @@ assert t.data[1].d[0] 0 assert t.data[1].d[1] 0 cycle system "echo '[1] reset completed'" +system "echo '----------------------------------------------------------'" + # Set delay config lines set t.dly_cfg[0] 1 set t.dly_cfg[1] 1 cycle -assert-qdi-channel-neutral "t.in" 5 system "echo '[2] delay line set'" -set-qdi-channel-valid "t.in" 5 19 +system "echo '----------------------------------------------------------'" + +set-qdi-channel-valid "t.in" 5 3 cycle assert-qdi-channel-valid "t.registers._in_write" 4 3 assert t.registers._clock 0 @@ -42,8 +40,10 @@ cycle set-qdi-channel-neutral "t.in" 5 cycle assert t.registers._clock 1 -assert t.registers.ff[0].q 1 -assert t.registers.ff[1].q 1 -system "echo '[3] clock checked'" +assert t.registers.ff_t[0].q 1 +assert t.registers.ff_t[1].q 1 +system "echo '[3] first writing done'" +system "echo '----------------------------------------------------------'" +