diff --git a/dataflow_neuro/chips_noread.act b/dataflow_neuro/chips_noread.act index eb32197..e8c2762 100644 --- a/dataflow_neuro/chips_noread.act +++ b/dataflow_neuro/chips_noread.act @@ -94,7 +94,8 @@ defproc texel_core (avMx1of2 in, out; demux_bit_msb _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply); // Register - fifo fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply); + slice_data slice_pre_reg(.in = _demux.out2, .supply = supply); + fifo fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply); register_w_array register(.in = fifo_dmx2reg.out, .data = reg_data, .supply = supply, .reset_B = reset_reg_B); diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 541c9d5..9ab2d10 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -841,17 +841,22 @@ defproc slice_data(avMx1of2 in; avMx1of2 out; _N1 = std::min(N1,N); _N0 = std::max(N0,0); + [_N0 = 0 & _N1 = N -> + in = out; + [] _N0 != 0 | _N1 != N -> - // BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd); + vtree in_vt(.in = in.d, .out = in.v, .supply = supply); + (i:_N1-_N0: + in.d.d[i + _N0] = out.d.d[i]; + ) - vtree in_vt(.in = in.d, .out = in.v, .supply = supply); - (i:_N1-_N0: - in.d.d[i + _N0] = out.d.d[i]; - ) + // in.a = out.a; + + A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd); + + ] - // in.a = out.a; - A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd); } diff --git a/test/unit_tests/texel_dualcore_glue_noread/test.act b/test/unit_tests/texel_dualcore_glue_noread/test.act index 770236e..704110f 100644 --- a/test/unit_tests/texel_dualcore_glue_noread/test.act +++ b/test/unit_tests/texel_dualcore_glue_noread/test.act @@ -75,7 +75,7 @@ pint N_LINE_PD_DLY = 2; pint REG_NCA = 6; pint REG_M = 1< in, out; diff --git a/test/unit_tests/texel_dualcore_glue_noread/test.prsim b/test/unit_tests/texel_dualcore_glue_noread/test.prsim index fa7ebbc..37bc3d1 100644 --- a/test/unit_tests/texel_dualcore_glue_noread/test.prsim +++ b/test/unit_tests/texel_dualcore_glue_noread/test.prsim @@ -50,8 +50,6 @@ watch c.c1_reg_data[0].d[21].t watch c.c1_reg_data[0].d[21].f watch c.c1_reg_data[0].d[22].t watch c.c1_reg_data[0].d[22].f -watch c.c1_reg_data[0].d[23].t -watch c.c1_reg_data[0].d[23].f set c.bd_dly_cfg[0] 1