From 596a6f9c9fc34582aa4ab906b59ea933373b1938 Mon Sep 17 00:00:00 2001 From: alexmadison Date: Fri, 1 Apr 2022 18:10:49 +0200 Subject: [PATCH] register A cell init, compiling not tested --- dataflow_neuro/registers.act | 67 +++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index 974ba41..73a510d 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -266,6 +266,9 @@ export template defproc buffer_register(avMx1of2 in; Mx1of2 out; bool? out_v, flush, reset_B; power supply) { +// BIG TODO +// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET + //control bool _en, _reset_BX,_reset_BXX[N]; bool _in_aB; @@ -312,7 +315,6 @@ sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); f_buf_func[i].c1=_flushB; t_buf_func[i].c1=_flushB; - f_buf_func[i].n2=_en_X_f[i]; t_buf_func[i].n2=_en_X_t[i]; // f_buf_func[i].c2=_out_a_BX_f[i]; @@ -328,10 +330,73 @@ sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); f_buf_func[i].pr_B = _reset_BXX[i]; f_buf_func[i].sr_B = _reset_BXX[i]; ) +} +/** + * Register made out of A cells. + * last bit is whether to read or write. + * Currently only handles writing. + */ +export template +defproc registerA(avMx1of2 in; Mx1of2 out; + bool? reset_B; power supply) { + +// BIG TODO +// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET + +bool _en2; +bool _w; +bool _out_v, _out_vB; +bool _flush, _flushB; + +_w = in.d.d[N].t; + +// Buffer +buffer_register buf(.out = out, .out_v = _out_v, .flush = _flush, + .supply = supply, .reset_B = reset_B); +buf.in.v = in.v; + +// In ack stuff +INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss); +// To stop in ack going low before en2 has been reset. +A_1C1N_X1 in_ack_safety(.c1 = buf.in.a, .n1 = _en2, .y = in.a, + .vdd = supply.vdd, .vss = supply.vss); + +// Out valid tree +vtree out_valid(.in = buf.out, .out = _out_v, .supply = supply); +INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss); + +// Control +A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush, + .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B); +INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss); + +A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2); + +// Pass to let data into the buffer +NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd); +AND2_X1 gandalf_t[N]; +AND2_X1 gandalf_f[N]; +(i:0..N-1: + gandalf_t[i].a = in.d.d[i].t; + gandalf_f[i].a = in.d.d[i].f; + gandalf_t[i].b = pass.y; + gandalf_f[i].b = pass.y; + gandalf_t[i].y = buf.in.d.d[i].t; + gandalf_f[i].y = buf.in.d.d[i].f; + + gandalf_t[i].vdd = supply.vdd; + gandalf_f[i].vdd = supply.vdd; + gandalf_t[i].vss = supply.vss; + gandalf_f[i].vss = supply.vss; + + +) + } + }}