From 5aab3d2d3b111f9d8bca69fa9017a58f96072dc1 Mon Sep 17 00:00:00 2001
From: alexmadison <git@mdsn.co.uk>
Date: Sat, 9 Apr 2022 14:17:22 +0200
Subject: [PATCH] added ands on synapse x mon decoder, on DEV_DEBUG

---
 dataflow_neuro/chips.act | 32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act
index 3aa82d0..c2e87c3 100644
--- a/dataflow_neuro/chips.act
+++ b/dataflow_neuro/chips.act
@@ -133,34 +133,58 @@ defproc chip_texel (bd<N_IN> in, out;
     pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
     pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
 
-    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X, N_NRN_Y> nrn_mon_dec_x(.out = nrn_mon_x,
+    decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.out = nrn_mon_x,
         .supply = supply);
     nrn_mon_dec_x.en = register.data[1].d[0].t;
     (i:NC_NRN_MON_X:
         nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
     )
 
-    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y, N_NRN_X> nrn_mon_dec_y(.out = nrn_mon_y,
+    decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.out = nrn_mon_y,
         .supply = supply);
     nrn_mon_dec_y.en = register.data[1].d[0].t;
     (i:NC_NRN_MON_Y:
         nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
     )
 
-    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X, N_SYN_Y> syn_mon_dec_x(.out = syn_mon_x,
+    decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
         .supply = supply);
     syn_mon_dec_x.en = register.data[1].d[1].t;
     (i:NC_SYN_MON_X:
         syn_mon_dec_x.in.d[i] = register.data[3].d[i];
     )
 
-    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y, N_SYN_X> syn_mon_dec_y(.out = syn_mon_y,
+    decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.out = syn_mon_y,
         .supply = supply);
     syn_mon_dec_y.en = register.data[1].d[1].t;
     (i:NC_SYN_MON_Y:
         syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
     )
 
+    // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
+    // Stops the possibility of dev_mon being high while some other sig is high.
+    // Otherwise boom.
+    bool DEV_DEBUG;
+    pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
+    sigbuf<NSMX4> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
+        .supply = supply);
+    DEV_DEBUG = sb_DEV_DEBUG.out[0];
+    AND2_X1 ands_devmon[NSMX4];
+    (i:NSMX4:
+        ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
+        ands_devmon[i].b = DEV_DEBUG;
+        ands_devmon[i].y = syn_mon_x[1+i*4];
+        ands_devmon[i].vdd = supply.vdd;
+        ands_devmon[i].vss = supply.vss;
+    )
+    // Wire up the non-ANDed lines.
+    (i:N_SYN_MON_X:
+        [~(i%4 = 1) ->
+            syn_mon_x[i] = syn_mon_dec_x.out[i];
+        ]
+    )
+
+
 }
 }
 }