diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act index c017a41..c57ed49 100644 --- a/dataflow_neuro/cell_lib_async.act +++ b/dataflow_neuro/cell_lib_async.act @@ -193,12 +193,12 @@ namespace tmpl { y {-1}} } - export defcell A_2C2N_R_B_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss) + export defcell A_2C2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss) { bool _y; prs{ - (~c1 & ~c2) | ~rp_B -> _y+ - c1 & c2 & n1 & n2 & rs_B -> _y- + (~c1 & ~c2) | ~pr_B -> _y+ + c1 & c2 & n1 & n2 & sr_B -> _y- _y => y- } sizing { @@ -207,12 +207,12 @@ namespace tmpl { y {-1}; _y{-1}} } - export defcell A_2C2N_R_B_X2 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss) + export defcell A_2C2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss) { bool _y; prs{ - (~c1 & ~c2) | ~rp_B -> _y+ - c1 & c2 & n1 & n2 & rs_B -> _y- + (~c1 & ~c2) | ~pr_B -> _y+ + c1 & c2 & n1 & n2 & sr_B -> _y- _y => y- } sizing { @@ -221,12 +221,12 @@ namespace tmpl { y {-2}; _y{-1}} } - export defcell A_2C2N_R_B_X4 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss) + export defcell A_2C2N_RB_X4 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss) { bool _y; prs{ - (~c1 & ~c2) | ~rp_B -> _y+ - c1 & c2 & n1 & n2 & rs_B -> _y- + (~c1 & ~c2) | ~pr_B -> _y+ + c1 & c2 & n1 & n2 & sr_B -> _y- _y => y- } sizing { @@ -236,11 +236,11 @@ namespace tmpl { } - export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss) + export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss) { prs{ - (~c1 & ~c2) | ~rp_B -> y+ - c1 & c2 & n1 & n2 & rs_B -> y- + (~c1 & ~c2) | ~pr_B -> y+ + c1 & c2 & n1 & n2 & sr_B -> y- } sizing { leak_adjust <- 1; @@ -276,6 +276,20 @@ namespace tmpl { y {-1}; _y{-1}} } + export defcell A_2C_RB_X4 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss) + { + bool _y; + prs{ + (~c1 & ~c2) | ~pr_B -> _y+ + c1 & c2 & sr_B -> _y- + _y => y- + } + sizing { + leak_adjust <- 1; + p_n_mode <- 1; + y {-4}; _y{-1}} + } + export defcell A_2C_R_X1 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss) { prs{ diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 778bbf3..40f8ba5 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -4,7 +4,7 @@ * * Copyright (c) 2022 University of Groningen - Ole Richter * Copyright (c) 2022 University of Groningen - Michele Mastella - * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Hugh Greatorex * * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * @@ -104,7 +104,7 @@ namespace tmpl { * */ export template - defproc buffer (avMx1of2 in; avMx1of2 out; bool? reset_B, c_f, c_t; power supply) { + defproc buffer (avMx1of2 in; avMx1of2 out; bool? reset_B; power supply) { //control bool _en, _reset_BX,_reset_BXX[N]; A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); @@ -150,67 +150,92 @@ namespace tmpl { ) } - // export template - // defproc demux (avMx1of2 in; avMx1of2 out; bool? reset_B; power supply) { - // //control - // bool _en, _reset_BX,_reset_BXX[N]; - // OR2_X1 out_or(.a=out.v1, .b=out.v2,.vdd=supply.vdd,.vss=supply.vss); - // A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); - - // //validity - // BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); - // sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); + export template + defproc demux (avMx1of2 in; avMx1of2 out1; avMx1of2 out2; bool? reset_B, c_t, c_f; power supply) { + //control + bool _en, _reset_BX,_reset_BXX[N], _out_v; + OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss); + A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); + A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); + A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); - // A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + //validity + bool _in_v, _c_f_buf, _c_t_buf, _c_v, _in_c_v_; + + sigbuf c_buf_t(.in=c_t, .out=_c_t_buf); + sigbuf c_buf_f(.in=c_f, .out=_c_f_buf); + + OR2_X1 c_f_c_t_or(.a=c_t, .b=c_f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss); + ctree vc(.in=in.d,.out=_in_v,.supply=supply); + + A_2C_RB_X4 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss); + BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); + + + //function + //func buffer out1 + bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N]; + A_2C2N_RB_X4 out1_f_buf_func[N]; + A_2C2N_RB_X4 out1_t_buf_func[N]; + sigbuf out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply); + sigbuf out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply); + INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B); + sigbuf out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t); + sigbuf out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f); + (i:N: + out1_f_buf_func[i].y=out1.d.d[i].f; + out1_t_buf_func[i].y=out1.d.d[i].t; + out1_f_buf_func[i].c1=_en1_X_f[i]; + out1_t_buf_func[i].c1=_en1_X_t[i]; + out1_f_buf_func[i].c2=_out1_a_BX_f[i]; + out1_t_buf_func[i].c2=_out1_a_BX_t[i]; + out1_f_buf_func[i].n1=in.d.d[i].f; + out1_t_buf_func[i].n1=in.d.d[i].t; + out1_f_buf_func[i].vdd=supply.vdd; + out1_t_buf_func[i].vdd=supply.vdd; + out1_f_buf_func[i].vss=supply.vss; + out1_t_buf_func[i].vss=supply.vss; + out1_t_buf_func[i].pr_B = _reset_BXX[i]; + out1_t_buf_func[i].sr_B = _reset_BXX[i]; + out1_f_buf_func[i].pr_B = _reset_BXX[i]; + out1_f_buf_func[i].sr_B = _reset_BXX[i]; + out1_f_buf_func[i].n2=_c_t_buf; + out1_t_buf_func[i].n2=_c_t_buf; + ) + //func buffer out2 + bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N]; + A_2C2N_RB_X4 out2_f_buf_func[N]; + A_2C2N_RB_X4 out2_t_buf_func[N]; + sigbuf out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply); + sigbuf out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply); + INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B); + sigbuf out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t); + sigbuf out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f); + (i:N: + out2_f_buf_func[i].y=out2.d.d[i].f; + out2_t_buf_func[i].y=out2.d.d[i].t; + out2_f_buf_func[i].c1=_en2_X_f[i]; + out2_t_buf_func[i].c1=_en2_X_t[i]; + out2_f_buf_func[i].c2=_out2_a_BX_f[i]; + out2_t_buf_func[i].c2=_out2_a_BX_t[i]; + out2_f_buf_func[i].n1=in.d.d[i].f; + out2_t_buf_func[i].n1=in.d.d[i].t; + out2_f_buf_func[i].vdd=supply.vdd; + out2_t_buf_func[i].vdd=supply.vdd; + out2_f_buf_func[i].vss=supply.vss; + out2_t_buf_func[i].vss=supply.vss; + out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1]; + out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1]; + out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1]; + out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1]; + out2_f_buf_func[i].n2=_c_f_buf; + out2_t_buf_func[i].n2=_c_f_buf; + ) - // //validity - // bool _in_v, _c_f_buf, _c_t_buf, _c_v; - // sigbuf c_buf_t(.in=c_t, .out=_c_t_buf) - // sigbuf c_buf_f(.in=c_f, .out=_c_f_buf) - - // OR2_X1 c_f_c_t_or(.a=_c_t_buf, .b=_c_f_buf, out._c_v) - // ctree vc(.in=in.d,.out=_in_v,.supply=supply); - - - - - - // BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); - - - // //function - // bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N]; - // A_2C1N_RB_X4 f_buf_func[N]; - // A_2C1N_RB_X4 t_buf_func[N]; - // sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); - // sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); - // INV_X1 out_a_inv(.a=out.a,.y=_out_a_B); - // sigbuf out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t); - // sigbuf out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f); - // // check if you can also do single var to array connect a=b[N] - // // and remove them from the loop - // (i:N: - // f_buf_func[i].y=out.d.d[i].f; - // t_buf_func[i].y=out.d.d[i].t; - // f_buf_func[i].c1=_en_X_f[i]; - // t_buf_func[i].c1=_en_X_t[i]; - // f_buf_func[i].c2=_out_a_BX_f[i]; - // t_buf_func[i].c2=_out_a_BX_t[i]; - // f_buf_func[i].n1=in.d.d[i].f; - // t_buf_func[i].n1=in.d.d[i].t; - // f_buf_func[i].vdd=supply.vdd; - // t_buf_func[i].vdd=supply.vdd; - // f_buf_func[i].vss=supply.vss; - // t_buf_func[i].vss=supply.vss; - // t_buf_func[i].pr_B = _reset_BXX[i]; - // t_buf_func[i].sr_B = _reset_BXX[i]; - // f_buf_func[i].pr_B = _reset_BXX[i]; - // f_buf_func[i].sr_B = _reset_BXX[i]; - // ) - // } - - + } export template @@ -220,6 +245,7 @@ namespace tmpl { bool _en, _reset_BX,_reset_BXX[N*2]; A_4C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out1.v,.c4=out2.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); A_1C2P_X1 en_ctl(.c1=in.a,.p1=out1.v,.p2=out2.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + //reset_buffers BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);