diff --git a/dataflow_neuro/dynapse.act b/dataflow_neuro/dynapse.act
new file mode 100644
index 0000000..eac6563
--- /dev/null
+++ b/dataflow_neuro/dynapse.act
@@ -0,0 +1,66 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ * 
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/registers.act";
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/interfaces.act";
+// import tmpl::dataflow_neuro;
+// import tmpl::dataflow_neuro;
+import std::channel;
+open std::channel;
+
+namespace tmpl {
+    namespace dataflow_neuro {
+
+
+export
+defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
+	bool _en;
+	bool _out_a_B;
+
+	INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
+
+	A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
+		.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
+
+	A_1C1P_X1 A_en(.c1 = in.a, .p1 =  out.r, .y = _en,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+}
+
+}
+}
+
diff --git a/test/unit_tests/sadc_hs/test.act b/test/unit_tests/sadc_hs/test.act
new file mode 100644
index 0000000..e9a6500
--- /dev/null
+++ b/test/unit_tests/sadc_hs/test.act
@@ -0,0 +1,67 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/dynapse.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+defproc _sadc_hs (a1of1 in[4], out; bool? reset_B) {
+
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    // pipe loads of inputs into the sadc handshake
+    // to simulate a neuron going nuts
+    fifo_t<3> in_fifos[4];
+    arbtree<4> in_arbtree(.supply = supply);
+
+    (i:4:
+        in_fifos[i].in = in[i];
+        in_fifos[i].reset_B = reset_B;
+        in_fifos[i].out = in_arbtree.in[i];
+        in_fifos[i].supply = supply;
+    )
+
+    sadc_hs c(.in = in_arbtree.out,
+        .reset_B = reset_B, .supply = supply);
+
+    fifo_t<8> out_fifo(.in = c.out, .out = out,
+        .supply = supply, .reset_B = reset_B);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+_sadc_hs c; 
diff --git a/test/unit_tests/sadc_hs/test.prsim b/test/unit_tests/sadc_hs/test.prsim
new file mode 100644
index 0000000..7cd5a45
--- /dev/null
+++ b/test/unit_tests/sadc_hs/test.prsim
@@ -0,0 +1,72 @@
+watchall
+
+set c.reset_B 0
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+
+set c.out.a 0
+
+
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set c.reset_B 1
+cycle
+system "echo '[] Reset finished'"
+status X
+
+
+system "echo '[] Setting all in reqs high'"
+set c.in[0].r 1
+set c.in[1].r 1
+set c.in[2].r 1
+set c.in[3].r 1
+cycle
+
+assert c.in[0].a 1
+assert c.in[1].a 1
+assert c.in[2].a 1
+assert c.in[3].a 1
+
+set c.in[0].r 0
+set c.in[1].r 0
+set c.in[2].r 0
+set c.in[3].r 0
+cycle
+
+assert c.in[0].a 0
+assert c.in[1].a 0
+assert c.in[2].a 0
+assert c.in[3].a 0
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle
+
+assert c.out.r 1
+set c.out.a 1
+cycle
+assert c.out.r 0
+set c.out.a 0
+cycle