diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index 215e433..38e7767 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -51,8 +51,9 @@ namespace tmpl {
 //        - the last wl the word to write
 // data -> the data saved in the flip flop, sized wl x nw
 export template<pint log_nw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
+defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
     bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
+    pint _nw = 2<<log_nw;
     //Validation of the input 
     Mx1of2<1+log_nw+wl> in_temp;
     (i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
@@ -60,53 +61,50 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
     sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
     in.v = _in_v_temp;
     // Generation of the clock pulse
-    delayprog<N_dly_cfg> dly(.in = _in_v_temp, .s = _clock_temp, .supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _clock_temp,.out = _clock,.supply = supply);
+    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
+    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
     // Sending back to the ackowledge
-    delayprog<N_dly_cfg> dly(.in = _clock, .s = _in_a_temp, .supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
+    delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
+    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
     //Reset Buffers
-    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*w];
-    BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_BXX_mem,.vdd=supply.vdd,.vss=supply.vss);
+    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
+    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
+    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
     // Creating the different flip flop arrays
-    bool _nw = 2<<log_nw;
-    bool _word_idx = 0;
     bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
     andtree<log_nw> atree[_nw];
     AND2_X1 and_encoder[_nw];
-    sigbuf<wl> clock_buffer;
+    sigbuf<wl> clock_buffer[_nw];
     DFFQ_R_X1 ff[_nw*wl];
-    (k:_nw:atree_x[k].supply = supply;)
+    pint _bitval;
+    (k:_nw:atree[k].supply = supply;)
     (_word_idx:_nw:
         // Decoding the bit pattern to understand which word we are looking at
         (pin_idx:log_nw:
-            bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
+            _bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
+            [_bitval = 1 -> 
                 atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t;
-            [] bitval = 0 ->
+            [] _bitval = 0 ->
                 atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f;
-            []bitval >= 2 -> {false : "fuck"};
+            []_bitval >= 2 -> {false : "fuck"};
             ]
         )
         // Activating the fake clock for the right word
-        atree_x[_word_idx].out = _out_encoder[_word_idx];    
+        atree[_word_idx].out = _out_encoder[_word_idx];    
         and_encoder[_word_idx].a = _out_encoder[_word_idx];
         and_encoder[_word_idx].b = _clock;
         and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
         and_encoder[_word_idx].vdd = supply.vdd;
         and_encoder[_word_idx].vss = supply.vss;
         clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
-        clock_buffer[_word_idx].out = _clock_word[_word_idx];
-        clock_buffer[_word_idx].vdd = supply.vdd;
-        clock_buffer[_word_idx].vss = supply.vss;
+        clock_buffer[_word_idx].supply = supply;
         // Describing all the FF and their connection
         (_bit_idx:wl:
-            ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx];
-            ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw];
+            ff[_bit_idx*(1+_word_idx)].clk = clock_buffer[_word_idx].out[_bit_idx];
+            ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
             ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
-            ff[_bit_idx*(1+_word_idx)].reset_B = reset_mem_BXX[_bit_idx*(1+_word_idx)];
+            ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
             ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
             ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
         )