From 790622bf955d7f5bdea73257429fb334686bb4a8 Mon Sep 17 00:00:00 2001 From: alexmadison Date: Tue, 12 Apr 2022 15:43:46 +0200 Subject: [PATCH] added nrn/syn output TBUFs, added nrn/syn EFO flag inputs --- dataflow_neuro/chips.act | 70 ++++++++++++++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 13 deletions(-) diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act index 5091cd0..a935784 100644 --- a/dataflow_neuro/chips.act +++ b/dataflow_neuro/chips.act @@ -47,7 +47,8 @@ N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y, N_SYN_DLY_CFG, N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y, -N_MON_AMZO_PER_SYN, // Number of signals that each synapse outputs to be monitored. +N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored. +N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register. N_BUFFERS, N_LINE_PD_DLY, // Number of dummy delays to add line pull down N_BD_DLY_CFG, N_BD_DLY_CFG2, @@ -57,10 +58,13 @@ defproc chip_texel (bd in, out; Mx1of2 reg_data[REG_M]; a1of1 synapses[N_SYN_X * N_SYN_Y]; a1of1 neurons[N_NRN_X * N_NRN_Y]; + bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y]; bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y]; - bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN]; // Synapse column monitor outputs - bool? syn_mon_AMO[N_MON_AMZO_PER_SYN]; + bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN]; + bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN]; + bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN]; + bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2]; bool? loopback_en; power supply; @@ -143,14 +147,14 @@ defproc chip_texel (bd in, out; (i:NC_NRN_MON_X: nrn_mon_dec_x.in.d[i] = register.data[2].d[i]; ) - sigbuf_boolarray nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply); + sigbuf_boolarray nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply); decoder_dualrail_en nrn_mon_dec_y(.supply = supply); nrn_mon_dec_y.en = register.data[1].d[0].t; (i:NC_NRN_MON_Y: nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X]; ) - sigbuf_boolarray nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply); + sigbuf_boolarray nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply); decoder_dualrail_en syn_mon_dec_x( .supply = supply); @@ -158,14 +162,14 @@ defproc chip_texel (bd in, out; (i:NC_SYN_MON_X: syn_mon_dec_x.in.d[i] = register.data[3].d[i]; ) - sigbuf_boolarray syn_mon_x_buf(.out = syn_mon_x, .supply = supply); + sigbuf_boolarray syn_mon_x_buf(.out = syn_mon_x, .supply = supply); decoder_dualrail_en syn_mon_dec_y(.supply = supply); syn_mon_dec_y.en = register.data[1].d[1].t; (i:NC_SYN_MON_Y: syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X]; ) - sigbuf_boolarray syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply); + sigbuf_boolarray syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply); // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG) // Stops the possibility of dev_mon being high while some other sig is high. @@ -193,19 +197,59 @@ defproc chip_texel (bd in, out; ] // Create TBUFs for each synapse column, - // ctrl wired to mon line (0'th in each 4). - pint N_TBUF = N_SYN_X * N_MON_AMZO_PER_SYN; - TBUF_X4 syn_x_AMZI_tbuf[N_TBUF]; - (i:N_SYN_X: - (j:N_MON_AMZO_PER_SYN: + // ctrl wired to mon line (first in each 4). + TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN]; + sigbuf_boolarray syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply); + (j:N_MON_AMZO_PER_SYN: + (i:N_SYN_X: index = i*N_MON_AMZO_PER_SYN + j; syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index]; syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4]; - syn_x_AMZI_tbuf[index].y = syn_mon_AMO[j]; + syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j]; ) ) + // Create TBUFs for each neuron column, + // ctrl wired to mon line (first in each 4). + TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN]; + sigbuf_boolarray nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply); + (j:N_MON_AMZO_PER_NRN: + (i:N_NRN_X: + index = i*N_MON_AMZO_PER_NRN + j; + nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index]; + nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2]; + nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j]; + ) + ) + + // Create NON buffered signals from register to nrns. + (i:N_FLAGS_PER_NRN: + nrn_flags_EFO[i] = register.data[5].d[i].t; + ) + + // Create NON buffered signals from register to synapses. + // Includes safety on the first 3 flags with dev mon. + (i:3..N_FLAGS_PER_SYN-1: + syn_flags_EFO[i] = register.data[4].d[i].t; + ) + AND2_X1 syn_flags_dev_safety[3]; + BUF_X4 syn_flags_dev_safety_sb[3]; + (i:0..2: + syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit + syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored. + syn_flags_dev_safety_sb[i].a = syn_flags_dev_safety[i].y; + syn_flags_dev_safety_sb[i].y = syn_flags_EFO[i]; + + syn_flags_dev_safety[i].vdd = supply.vdd; + syn_flags_dev_safety[i].vss = supply.vss; + syn_flags_dev_safety_sb[i].vdd = supply.vdd; + syn_flags_dev_safety_sb[i].vss = supply.vss; + ) + + + +