From 7e86815e28a3dfc053d0a1fc02992579acc29028 Mon Sep 17 00:00:00 2001 From: Hugh Date: Tue, 22 Feb 2022 13:52:54 +0100 Subject: [PATCH] attempting to complete the buffer --- dataflow_neuro/cell_lib_async.act | 2 +- dataflow_neuro/primitives.act | 44 ++++++++++++++------------- dataflow_neuro/treegates.act | 25 +++++++-------- test/unit_tests/buf_15/run/test.prs | 3 ++ test/unit_tests/buf_15/test.act | 47 +++++++++++++++++++++++++++++ test/unit_tests/buf_15/test.prsim | 16 ++++++++++ test/unit_tests/init.prs | 1 + test/unit_tests/init_qdi.prsim | 1 + 8 files changed, 105 insertions(+), 34 deletions(-) create mode 100644 test/unit_tests/buf_15/run/test.prs create mode 100644 test/unit_tests/buf_15/test.act create mode 100644 test/unit_tests/buf_15/test.prsim diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act index 9e97175..aa16479 100644 --- a/dataflow_neuro/cell_lib_async.act +++ b/dataflow_neuro/cell_lib_async.act @@ -79,7 +79,7 @@ namespace tmpl { } - export defcell A_1C1P (bool! y; bool? c1, p1; bool vdd, vss) + export defcell A_1C1P_X1 (bool! y; bool? c1, p1; bool vdd, vss) { prs{ ~p1 & ~c1 -> y+ diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index e4c33e1..b12144f 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -2,7 +2,9 @@ * * This file is part of ACT dataflow neuro library * - * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Hugh Greatorex * * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * @@ -21,8 +23,9 @@ * ************************************************************************** */ -import "cell_lib_async.act"; -import "cell_lib_std.act"; +import "../../dataflow_neuro/cell_lib_async.act"; +import "../../dataflow_neuro/cell_lib_std.act"; +import "../../dataflow_neuro/treegates.act"; // import tmpl::dataflow_neuro; // import tmpl::dataflow_neuro; import std::channel; @@ -101,26 +104,25 @@ namespace tmpl { * */ export template - defproc buffer (avMx1of2 in; avMx1of2 out; rsp reset; power supply) { + defproc buffer (avMx1of2 in; avMx1of2 out; bool? reset_B; power supply) { //control - bool _en,_en_X,_preset_X,_sreset_X; - A_3C_RB_X4 inack_ctl(c1=en_X,c2=in.v,c3=out.v,y=in.a,pr_B=_preset_X,sr_B=_sreset_X,vdd=supply.vdd,vss=supply.vss); - A_1C1P_X1 en_ctl(c1=in.a,p1=out.v,y=_en,vdd=supply.vdd,vss=supply.vss); - sigbuf en_buf(a=_en, y=_en_X, power=supply); - sigbuf preset_buf(a=reset.p,y=preset_X, power=supply); - sigbuf sreset_buf(a=reset.s,y=sreset_X, power=supply); - + bool _en,_en_X, _reset_BX,_reset_BXX[N]; + A_3C_RB_X4 inack_ctl(.c1=_en_X,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=reset_B,.sr_B=reset_B,.vdd=supply.vdd,.vss=supply.vss); + A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); + sigbuf en_buf(.in=_en, .out=_en_X, .supply=supply); + sigbuf reset_bufarray(.in=reset_BX, .out=_reset_BXX); + BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX); //validity bool _in_v; - ctree vc(in=in.d,y=_in_v, power=supply); - sigbuf in_v_buf<12>(a=_in_v, y=in.v); + ctree vc(.in=in.d,.y=_in_v,.vdd=supply.vdd,.vss=supply.vss); + sigbuf<12> in_v_buf(.in=_in_v, .out=in.v,.vdd=supply.vdd,.vss=supply.vss); //function bool _out_a_BX, _out_a_B; - A_2C1N_RB_X4 f_buf_func[N]; + A_2C1N_RB_X4 f_buf_func[N](.pr_B = reset_BXX,.sr_B = reset_BXX); A_2C1N_RB_X4 t_buf_func[N]; - INV_X1 out_a_inv(a=out.a,y=_out_a_B); - sigbuf out_a_B_buf(a=_out_a_B,y=_out_a_BX); + INV_X1 out_a_inv(.a=out.a,.y=_out_a_B); + sigbuf out_a_B_buf(.a=_out_a_B,.y=_out_a_BX); // check if you can also do single var to array connect a=b[N] // and remove them from the loop (i:N: @@ -132,10 +134,10 @@ namespace tmpl { t_buf_func[i].c2=_out_a_BX; f_buf_func[i].n1=in.d.d[i].f; t_buf_func[i].n1=in.d.d[i].t; - f_buf_func[i].pr_B=_preset_X; - t_buf_func[i].pr_B=_preset_X; - f_buf_func[i].sr_B=_sreset_X; - t_buf_func[i].sr_B=_sreset_X; + f_buf_func[i].pr_B=reset_B; + t_buf_func[i].pr_B=reset_B; + f_buf_func[i].sr_B=reset_B; + t_buf_func[i].sr_B=reset_B; f_buf_func[i].vdd=supply.vdd; t_buf_func[i].vdd=supply.vdd; f_buf_func[i].vss=supply.vss; @@ -143,4 +145,4 @@ namespace tmpl { ) } } -} \ No newline at end of file +} diff --git a/dataflow_neuro/treegates.act b/dataflow_neuro/treegates.act index dc8474e..044cf24 100644 --- a/dataflow_neuro/treegates.act +++ b/dataflow_neuro/treegates.act @@ -247,28 +247,29 @@ defproc ctree (bool? in[N]; bool! out; power supply) } export template -defproc sigbuf (bool? in; bool! out; power supply) +defproc sigbuf (bool? in; bool! out[N]; power supply) { { N >= 0 : "sigbuf: parameter error" }; { N <= 43 : "sigbuf: parameter error, N too big" }; - /* -- just use a sized driver here -- */ - [ N <= 4 -> - BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); - [] N >= 5 & N <= 7 -> - BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); - [] N >= 8 & N <= 10 -> - BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + /* -- just use in sized driver here -- */ + [ N <= 4 -> + BUF_X1 buf1 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); + [] N >= 5 & N <= 7 -> + BUF_X2 buf2 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); + [] N >= 8 & N <= 10 -> + BUF_X3 buf3 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); [] N >= 11 & N <= 14 -> - BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + BUF_X4 buf4 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); [] N >= 15 & N <= 18 -> - BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); [] N >= 19 & N <= 29 -> - BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); [] N >= 30 & N <= 42 -> - BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); + BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss); ] + (i:1..N:y[i]=y[0];) } }} diff --git a/test/unit_tests/buf_15/run/test.prs b/test/unit_tests/buf_15/run/test.prs new file mode 100644 index 0000000..02d06ef --- /dev/null +++ b/test/unit_tests/buf_15/run/test.prs @@ -0,0 +1,3 @@ += "GND" "GND" += "Vdd" "Vdd" += "Reset" "Reset" diff --git a/test/unit_tests/buf_15/test.act b/test/unit_tests/buf_15/test.act new file mode 100644 index 0000000..ef41ec1 --- /dev/null +++ b/test/unit_tests/buf_15/test.act @@ -0,0 +1,47 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/primitives.act"; +import globals; + +open tmpl::dataflow_neuro; + +defproc buffer_15 (avMx1of2 in; avMx1of2 out){ + + buffer<15> buffer_test(.in=in, .out=out, .reset_B = Reset); + //Low active Reset + bool _reset_B; + prs { + Reset => _reset_B- + } + buffer_test.supply.vss = GND; + buffer_test.supply.vdd = Vdd; + +} + +buffer_15 t; diff --git a/test/unit_tests/buf_15/test.prsim b/test/unit_tests/buf_15/test.prsim new file mode 100644 index 0000000..7c9db4f --- /dev/null +++ b/test/unit_tests/buf_15/test.prsim @@ -0,0 +1,16 @@ + +set-channel-neutral "t.in" 15 +set t.out.a 0 +set t.out.v 0 + +system "echo 'yo man'" + +set t.reset 1 + +cycle +system "echo 'reset completed'" +status X +mode run +cycle + +assert t.out.d 0 diff --git a/test/unit_tests/init.prs b/test/unit_tests/init.prs index 1e7d3e0..02d06ef 100644 --- a/test/unit_tests/init.prs +++ b/test/unit_tests/init.prs @@ -1,2 +1,3 @@ = "GND" "GND" = "Vdd" "Vdd" += "Reset" "Reset" diff --git a/test/unit_tests/init_qdi.prsim b/test/unit_tests/init_qdi.prsim index 91fe00e..5260a9d 100644 --- a/test/unit_tests/init_qdi.prsim +++ b/test/unit_tests/init_qdi.prsim @@ -3,6 +3,7 @@ load-scm "helper.scm" random set GND 0 set Vdd 1 +set Reset 0 mode reset cycle