diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act
index 1dc3155..1163d07 100644
--- a/dataflow_neuro/cell_lib_async.act
+++ b/dataflow_neuro/cell_lib_async.act
@@ -26,6 +26,33 @@
 
 namespace tmpl {
     namespace dataflow_neuro{
+        export defcell KEEP_X1 (bool y; bool vdd, vss) {
+            bool _y;
+            prs{
+                y => _y-
+                [weak=1] _y => y-
+                }
+            sizing {
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+                y {-1}; _y{-1} 
+                }
+        }
+
+        export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~c1)|~pr_B -> _y+
+                c1 & n1 & n2 & sr_B -> _y-
+                _y => y-
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             bool _y;
             prs{
@@ -41,6 +68,22 @@ namespace tmpl {
                     }
         }
 
+
+        export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
+            bool _y;
+            prs{
+                (~p1 & ~c1 & ~c2)|~pr_B -> _y+
+                c1 & c2 & n1 & sr_B -> _y-
+                _y => y-
+
+                }
+            sizing {
+                    leak_adjust <- 1; 
+                    p_n_mode <- 1;
+                    y {-1}; _y{-1} 
+                    }
+        }
+
         export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
             prs{
                 (~p1 & ~c1)|~pr_B -> y-
diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act
index c963043..0c09581 100644
--- a/dataflow_neuro/primitives.act
+++ b/dataflow_neuro/primitives.act
@@ -685,6 +685,31 @@ namespace tmpl {
             (i:((1<<N)-1):dly[i].vss = supply.vss;)
         }
 
+        // Non programmable delays
+        // N is number of delays to have in series (not log!!).
+        // Is useful for testing purposes.
+        // But should probably remove before running innovus etc.
+        export template<pint N>
+        defproc delay_fifo (bool! out; bool? in; power supply) {
+            { N >= 0 : "What?" };
+            DLY4_X1 dly[N];
+
+            dly[0].vdd = supply.vdd;
+            dly[0].vss = supply.vss;
+            dly[0].a = in;
+
+            (i:1..N-1:
+                dly[i].vdd = supply.vdd;
+                dly[i].vss = supply.vss;
+                dly[i].a = dly[i-1].y;
+            )
+
+            dly[N-1].vdd = supply.vdd;
+            dly[N-1].vss = supply.vss;
+            dly[N-1].y = out;
+        }
+
+
         /**
          * Appends a hard-coded word "VAL" to an input.
          * Works by piping through all sigs, but adding