diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act
index aa63854..972d578 100644
--- a/dataflow_neuro/cell_lib_async.act
+++ b/dataflow_neuro/cell_lib_async.act
@@ -204,6 +204,19 @@ namespace tmpl {
             y {-4}; _y{-1}}
         }
 
+        export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~c2 & ~sr-> _y+
+            c1&c2&n1 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
 
         export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
         {
diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index 1a5b42b..4924e94 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -172,82 +172,83 @@ AND2_X1 gandalf_f[N];
 
 }
 
-
-
-/** 
- * Array of registers made out of A-cells
- * params:
- * NcW: number of bits in Words to be stored in buffers
- * NcA: number of bits in Address
- * M: number of registers.  M = 2^Nc_addr would be a natural choice.
- * Input packets should be 
- * [-addr-][-word-][r/w]
+/**
+ * A single register made out of A cells.
+ * MSB is whether to read or write.
+ * Currently only handles writing.
+ * NOTE: this does not handle in.v properly, and instead has in.v = in.a
  */
+export template<pint N>
+defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
+    bool? reset_B; power supply) {
 
-// UNUSED
-// UNUSED
-// UNUSED
-// UNUSED
+bool _resetX[N], _reset_BX[N];
+bool _en, _enBX;
+bool _flush, _flushBX;
+bool _out_v, _out_vB;
+bool _w = in.d.d[N].t;
 
-// export template<pint NcA, NcW, M>
-// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
-//     bool? reset_B; power supply) {
+INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
+    .vdd = supply.vdd, .vss= supply.vss);
 
-// // BIG TODO
-// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
-// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
-//     .supply = supply);
+// Reset sigs
+INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
+sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
+
+A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
+    .vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
+
+A_2C_X1 A_en(.c1  = _w, .c2 = _out_vB, .y = _en,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
+sb_flushB.out[0] = _flushBX;
+
+INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
+sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
+sb_enB.out[0] = _enBX;
+
+vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
+
+// WARNING WARNING
+in.v = in.a;
+
+A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
+    .vdd = supply.vdd, .vss = supply.vss);
+
+//function
+A_2C1N_SB_X4 f_buf_func[N];
+A_2C1N_RB_X4 t_buf_func[N];
+(i:N: 
+    f_buf_func[i].y=out.d[i].f;
+    t_buf_func[i].y=out.d[i].t;
+
+    f_buf_func[i].c1=_flushBX;
+    t_buf_func[i].c1=_flushBX;
+
+    f_buf_func[i].c2=_enBX;
+    t_buf_func[i].c2=_enBX;
+    
+    f_buf_func[i].n1=in.d.d[i].f;
+    t_buf_func[i].n1=in.d.d[i].t;
+
+    f_buf_func[i].vdd=supply.vdd;
+    t_buf_func[i].vdd=supply.vdd;
+    f_buf_func[i].vss=supply.vss;
+    t_buf_func[i].vss=supply.vss;
+    
+    f_buf_func[i].pr = _resetX[i];
+    f_buf_func[i].sr = _resetX[i];
+    t_buf_func[i].pr_B = _reset_BX[i];
+    t_buf_func[i].sr_B = _reset_BX[i];
+)
+
+}
 
 
-// // Address decoder
-// decoder_dualrail<NcA, M> decoder(.supply = supply);
-// (i:NcA:
-//     decoder.in.d[i] = in.d.d[i];
-// )
 
-// // OrTree over acks from all registers
-// ortree<M> ack_ortree(.supply = supply);
-
-// // C element handling in ack
-// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
-//     .vss = supply.vss, .vdd = supply.vdd); 
-
-// // Write bit selector
-// bool _w = in.d.d[NcA+NcW].t;
-// A_2C_B_X1 write_selectors[M];
-// (i:M:
-//     write_selectors[i].c1 = _w;
-//     write_selectors[i].c2 = decoder.out[i];
-//     write_selectors[i].vdd = supply.vdd;
-//     write_selectors[i].vss = supply.vss;
-// )
-
-// // Registers
-// register_acells<NcW> registers[M];
-// TIELO_X1 tielow_writebit_f[M];
-// (i:M:
-//     // Connect each register to word inputs.
-//     (j:NcW:
-//         registers[i].in.d.d[j] = in.d.d[j + NcA];
-//     )
-
-//     // Connect the (selected) write bit
-//     registers[i].in.d.d[NcW].t = write_selectors[i].y;
-//     tielow_writebit_f[i].vdd = supply.vdd;
-//     tielow_writebit_f[i].vss = supply.vss;
-//     registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
-
-//     // Connect to ack ortree
-//     registers[i].in.a = ack_ortree.in[i];
-
-//     // Connect outputs
-//     data[i] = registers[i].out;
-
-//     registers[i].supply = supply;
-//     registers[i].reset_B = reset_B;
-// )
-
-// }
 
 /** 
  * Array of registers made out of A-cells
@@ -303,7 +304,7 @@ A_2C_B_X1 write_selectors[M];
 
 
 // Registers
-register_acells<NcW> registers[M];
+register_acells_improved<NcW> registers[M];
 TIELO_X1 tielow_writebit_f[M];
 (i:M:
     // Connect each register to word inputs.