diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act index ad7395d..f98b9b0 100644 --- a/dataflow_neuro/chips.act +++ b/dataflow_neuro/chips.act @@ -545,238 +545,6 @@ defproc texel_dualcore (bd in, out; -export template -defproc texel_dualcore_mapper (bd in, out; - - Mx1of2 c1_reg_data[REG_M]; - - bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y]; - bool? c1_dec_ackB[N_SYN_X]; - a1of1 c1_syn_pu[N_SYN_X]; - - a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y]; - a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y]; - - bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y]; - bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y]; - bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN]; - bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN]; - bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN]; - - bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X], - c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X]; - - Mx1of2 c2_reg_data[REG_M]; - - bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y]; - bool? c2_dec_ackB[N_SYN_X]; - a1of1 c2_syn_pu[N_SYN_X]; - - a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y]; - a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y]; - - bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y]; - bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y]; - bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN]; - bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN]; - bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN]; - - bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X], - c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X]; - - bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2]; - bool? loopback_en; - power supply; - bool? reset_B, reset_reg_B, reset_syn_stge_BI; - - // MAPPER STUFF - - bool? mapper_en; - avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr) - avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr) - avMx1of2<29> in_sram_r; // Readout packets from SRAM - avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr) - - ){ - - // Reset buffers - bool _reset_BX; - BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss); - - bd2qdi _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2, - .reset_B = _reset_BX, .supply = supply); - fifo fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply); - - fork _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply); - - // Loopback - fifo fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply); - dropper_static _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en, - .supply = supply); - fifo fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply); - - - - // dmx to SRAM - bool is_to_sram, is_to_cores; - fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX); - demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX); - sram_dmx.cond.d.d[0].t = is_to_sram; - sram_dmx.cond.d.d[0].f = is_to_cores; - AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t, - .y = is_to_sram, - .vdd = supply.vdd, .vss = supply.vss); - OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f, - .y = is_to_cores, - .vdd = supply.vdd, .vss = supply.vss); - slice_data<32, 0, 30> pre_sram_slice(.supply = supply); - pre_sram_slice.in.a = sram_dmx.out2.a; - pre_sram_slice.in.v = sram_dmx.out2.v; - (i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];) - pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31]; - pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30]; - pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29]; - fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr, - .reset_B = _reset_BX, .supply = supply); - - // spikes from sram - // requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx] - fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply); - append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply); - merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply); - merge_dmx8spk.in2.a = sram_spk_in_append.out.a; - merge_dmx8spk.in2.v = sram_spk_in_append.out.v; - (i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];) - merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13]; - (i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];) - - // Onwards to core demux - fifo fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply); - demux_bit_msb core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply); - fifo fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply); - fifo fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply); - - // Cores - texel_core - core1(.in = fifo_dmx2core1.out, - - .reg_data = c1_reg_data, - // .synapses = c1_synapses, - // .neurons = c1_neurons, - - .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y, - .dec_ackB = c1_dec_ackB, - .syn_pu = c1_syn_pu, - - .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny, - .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y, - - .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y, - .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y, - .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI, - .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO, - .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO, - - .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI, - .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO, - .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO, - - .supply = supply - ); - - - texel_core - core2(.in = fifo_dmx2core2.out, - - .reg_data = c2_reg_data, - // .synapses = c2_synapses, - // .neurons = c2_neurons, - - .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y, - .dec_ackB = c2_dec_ackB, - .syn_pu = c2_syn_pu, - - .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny, - .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y, - - .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y, - .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y, - .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI, - .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO, - .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO, - - .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI, - .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO, - .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO, - - .supply = supply - ); - - fifo fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply); - fifo fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply); - - // Merge cores - append append_core1(.in = fifo_core1out.out, .supply = supply); - append append_core2(.in = fifo_core2out.out, .supply = supply); - merge merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out, - .supply = supply, .reset_B = _reset_BX); - - - // fork after core merge then go to mapper if its a spike - fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply); - fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply); - dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply); - // Need to have it then drop the spike if its from a register. - demux_td<32, true> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data - drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30]; - drop_if_reg.token.r = drop_if_reg.token.a; - - slice_data<32,0,8> slice_to_sram(.supply = supply); - // And move the msb (core bit) to just after the neuron address... - slice_to_sram.in.a = drop_if_reg.out.a; - slice_to_sram.in.v = drop_if_reg.out.v; - (i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];) - slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31]; - (i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];) - - fifo<8,N_BUFFERS> fifo_out_sram_spk(.in = slice_to_sram.out, .out = out_sram_spk, - .reset_B = _reset_BX, .supply = supply); - - - // merge from cores and sram read in - fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply); - fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply); - append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply); - merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out, - .reset_B = _reset_BX, .supply = supply); - - // Merge cores and loopback - fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply); - merge merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out, - .reset_B = _reset_BX, .supply = supply); - - // qdi2bd - fifo fifo_mrg2bd(.in = merge_drop8core.out, - .reset_B = _reset_BX, .supply = supply); - qdi2bd _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg, - .reset_B = _reset_BX, .supply = supply); - -} - - - - -