From 8e38a0fb01c9c2d88303880b3f394fc0baebf6db Mon Sep 17 00:00:00 2001
From: alexmadison <git@mdsn.co.uk>
Date: Wed, 29 Jun 2022 15:58:58 +0200
Subject: [PATCH] put fake PRs in tiehi/los lol

---
 dataflow_neuro/cell_lib_std.act | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/dataflow_neuro/cell_lib_std.act b/dataflow_neuro/cell_lib_std.act
index 71fab0b..7afa277 100644
--- a/dataflow_neuro/cell_lib_std.act
+++ b/dataflow_neuro/cell_lib_std.act
@@ -27,14 +27,29 @@
 namespace tmpl {
   namespace dataflow_neuro {
 
+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
     export defproc TIELO_X1(bool! y; bool vdd, vss)
     {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
     }
 
     export defproc TIEHI_X1(bool! y; bool vdd, vss)
     {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
     }
 
     /*-- inverters --*/