From 97dacbfd08be8fccdd700574bb7a72f51af9d77f Mon Sep 17 00:00:00 2001 From: alexmadison Date: Wed, 15 Jun 2022 18:08:33 +0200 Subject: [PATCH] commented out old registers --- dataflow_neuro/registers.act | 184 +++++++++++++++++------------------ 1 file changed, 92 insertions(+), 92 deletions(-) diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index 4924e94..025bbb0 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -48,65 +48,65 @@ namespace tmpl { * Also, in.a does not wait for out.v to go low to go to low. * Means have a buffer that completes its Right handshake as soon as out data is valid. */ -export template -defproc buffer_register(avMx1of2 in; Mx1of2 out; bool? out_v, flush, - reset_B; power supply) { +// export template +// defproc buffer_register(avMx1of2 in; Mx1of2 out; bool? out_v, flush, +// reset_B; power supply) { -//control -bool _en, _reset_BX[N]; -bool _in_aB; +// //control +// bool _en, _reset_BX[N]; +// bool _in_aB; -bool _reset; -bool _resetX[N]; +// bool _reset; +// bool _resetX[N]; -// Reset sigs -INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); -sigbuf reset_sb(.in = _reset, .out = _resetX, .supply = supply); -sigbuf resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply); +// // Reset sigs +// INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); +// sigbuf reset_sb(.in = _reset, .out = _resetX, .supply = supply); +// sigbuf resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply); -A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, - .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss); +// A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, +// .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss); -INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); +// INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); -// Flush sigs -bool _flushB, _flushBX[N*2]; -INV_X1 flush_inv(.a = flush, .y = _flushB); -sigbuf flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); -_en = _in_aB; +// // Flush sigs +// bool _flushB, _flushBX[N*2]; +// INV_X1 flush_inv(.a = flush, .y = _flushB); +// sigbuf flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); +// _en = _in_aB; -//validity -bool _in_v; -vtree vc(.in=in.d,.out=_in_v,.supply=supply); -BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); +// //validity +// bool _in_v; +// vtree vc(.in=in.d,.out=_in_v,.supply=supply); +// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); -//function -bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; -A_1C2N_SB_X4 f_buf_func[N]; -A_1C2N_RB_X4 t_buf_func[N]; -sigbuf en_buf(.in=_en, .supply=supply); -(i:N: - f_buf_func[i].y=out.d[i].f; - t_buf_func[i].y=out.d[i].t; +// //function +// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; +// A_1C2N_SB_X4 f_buf_func[N]; +// A_1C2N_RB_X4 t_buf_func[N]; +// sigbuf en_buf(.in=_en, .supply=supply); +// (i:N: +// f_buf_func[i].y=out.d[i].f; +// t_buf_func[i].y=out.d[i].t; - f_buf_func[i].c1=_flushBX[i]; - t_buf_func[i].c1=_flushBX[i+N]; +// f_buf_func[i].c1=_flushBX[i]; +// t_buf_func[i].c1=_flushBX[i+N]; - f_buf_func[i].n2=en_buf.out[i]; - t_buf_func[i].n2=en_buf.out[i+N]; - f_buf_func[i].n1=in.d.d[i].f; - t_buf_func[i].n1=in.d.d[i].t; - f_buf_func[i].vdd=supply.vdd; - t_buf_func[i].vdd=supply.vdd; - f_buf_func[i].vss=supply.vss; - t_buf_func[i].vss=supply.vss; - f_buf_func[i].pr = _resetX[i]; - f_buf_func[i].sr = _resetX[i]; - t_buf_func[i].pr_B = _reset_BX[i]; - t_buf_func[i].sr_B = _reset_BX[i]; -) -} +// f_buf_func[i].n2=en_buf.out[i]; +// t_buf_func[i].n2=en_buf.out[i+N]; +// f_buf_func[i].n1=in.d.d[i].f; +// t_buf_func[i].n1=in.d.d[i].t; +// f_buf_func[i].vdd=supply.vdd; +// t_buf_func[i].vdd=supply.vdd; +// f_buf_func[i].vss=supply.vss; +// t_buf_func[i].vss=supply.vss; +// f_buf_func[i].pr = _resetX[i]; +// f_buf_func[i].sr = _resetX[i]; +// t_buf_func[i].pr_B = _reset_BX[i]; +// t_buf_func[i].sr_B = _reset_BX[i]; +// ) +// } /** @@ -114,63 +114,63 @@ sigbuf en_buf(.in=_en, .supply=supply); * MSB is whether to read or write. * Currently only handles writing. */ -export template -defproc register_acells(avMx1of2 in; Mx1of2 out; - bool? reset_B; power supply) { +// export template +// defproc register_acells(avMx1of2 in; Mx1of2 out; +// bool? reset_B; power supply) { -bool _en2; -bool _w; -bool _out_v, _out_vB; -bool _flush, _flushB; +// bool _en2; +// bool _w; +// bool _out_v, _out_vB; +// bool _flush, _flushB; -_w = in.d.d[N].t; +// _w = in.d.d[N].t; -// Buffer -buffer_register buf(.out = out, .out_v = _out_v, .flush = _flush, - .supply = supply, .reset_B = reset_B); -buf.in.v = in.v; +// // Buffer +// buffer_register buf(.out = out, .out_v = _out_v, .flush = _flush, +// .supply = supply, .reset_B = reset_B); +// buf.in.v = in.v; -// In ack stuff -INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss); -// To stop in ack going low before en2 has been reset. -A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a, - .vdd = supply.vdd, .vss = supply.vss); +// // In ack stuff +// INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss); +// // To stop in ack going low before en2 has been reset. +// A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a, +// .vdd = supply.vdd, .vss = supply.vss); -// Out valid tree -vtree out_valid(.in = buf.out, .out = _out_v, .supply = supply); -INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss); +// // Out valid tree +// vtree out_valid(.in = buf.out, .out = _out_v, .supply = supply); +// INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss); -// Control -A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush, - .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B); -INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss); +// // Control +// A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush, +// .vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B); +// INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss); -A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2, - .pr_B = reset_B, .sr_B = reset_B); +// A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2, +// .pr_B = reset_B, .sr_B = reset_B); -// Pass to let data into the buffer -NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd); -sigbuf passX(.in = pass.y, .supply = supply); -AND2_X1 gandalf_t[N]; -AND2_X1 gandalf_f[N]; -(i:0..N-1: - gandalf_t[i].a = in.d.d[i].t; - gandalf_f[i].a = in.d.d[i].f; - gandalf_t[i].b = passX.out[i]; - gandalf_f[i].b = passX.out[i+N]; - gandalf_t[i].y = buf.in.d.d[i].t; - gandalf_f[i].y = buf.in.d.d[i].f; +// // Pass to let data into the buffer +// NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd); +// sigbuf passX(.in = pass.y, .supply = supply); +// AND2_X1 gandalf_t[N]; +// AND2_X1 gandalf_f[N]; +// (i:0..N-1: +// gandalf_t[i].a = in.d.d[i].t; +// gandalf_f[i].a = in.d.d[i].f; +// gandalf_t[i].b = passX.out[i]; +// gandalf_f[i].b = passX.out[i+N]; +// gandalf_t[i].y = buf.in.d.d[i].t; +// gandalf_f[i].y = buf.in.d.d[i].f; - gandalf_t[i].vdd = supply.vdd; - gandalf_f[i].vdd = supply.vdd; - gandalf_t[i].vss = supply.vss; - gandalf_f[i].vss = supply.vss; +// gandalf_t[i].vdd = supply.vdd; +// gandalf_f[i].vdd = supply.vdd; +// gandalf_t[i].vss = supply.vss; +// gandalf_f[i].vss = supply.vss; -) +// ) -} +// } /** * A single register made out of A cells.