From a33bec178ff3dd2f2148ee4be2e31034afb4130e Mon Sep 17 00:00:00 2001 From: alexmadison Date: Sun, 10 Apr 2022 16:40:37 +0200 Subject: [PATCH] added TBUFs --- dataflow_neuro/chips.act | 42 ++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act index 9fa23f0..d60fca8 100644 --- a/dataflow_neuro/chips.act +++ b/dataflow_neuro/chips.act @@ -47,6 +47,7 @@ N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y, N_SYN_DLY_CFG, N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y, +N_MON_AMZO_PER_SYN, // Number of signals that each synapse outputs to be monitored. N_BUFFERS, N_LINE_PD_DLY, // Number of dummy delays to add line pull down N_BD_DLY_CFG, N_BD_DLY_CFG2, @@ -56,13 +57,17 @@ defproc chip_texel (bd in, out; Mx1of2 reg_data[REG_M]; a1of1 synapses[N_SYN_X * N_SYN_Y]; a1of1 neurons[N_NRN_X * N_NRN_Y]; - bool? nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y]; - bool? syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y]; + bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y]; + bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y]; + bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN]; // Synapse column monitor outputs + bool? syn_mon_AMO[N_MON_AMZO_PER_SYN]; bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2]; bool? loopback_en; power supply; bool? reset_B){ + pint index = 0; // Just useful + bd2qdi _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2, .reset_B = reset_B, .supply = supply); fifo fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply); @@ -133,19 +138,19 @@ defproc chip_texel (bd in, out; pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X); pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y); - decoder_dualrail_en nrn_mon_dec_x(.out = nrn_mon_x, - .supply = supply); + decoder_dualrail_en nrn_mon_dec_x(.supply = supply); nrn_mon_dec_x.en = register.data[1].d[0].t; (i:NC_NRN_MON_X: nrn_mon_dec_x.in.d[i] = register.data[2].d[i]; ) + sigbuf_boolarray nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply); - decoder_dualrail_en nrn_mon_dec_y(.out = nrn_mon_y, - .supply = supply); + decoder_dualrail_en nrn_mon_dec_y(.supply = supply); nrn_mon_dec_y.en = register.data[1].d[0].t; (i:NC_NRN_MON_Y: nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X]; ) + sigbuf_boolarray nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply); decoder_dualrail_en syn_mon_dec_x( .supply = supply); @@ -153,13 +158,14 @@ defproc chip_texel (bd in, out; (i:NC_SYN_MON_X: syn_mon_dec_x.in.d[i] = register.data[3].d[i]; ) + sigbuf_boolarray syn_mon_x_buf(.out = syn_mon_x, .supply = supply); - decoder_dualrail_en syn_mon_dec_y(.out = syn_mon_y, - .supply = supply); + decoder_dualrail_en syn_mon_dec_y(.supply = supply); syn_mon_dec_y.en = register.data[1].d[1].t; (i:NC_SYN_MON_Y: syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X]; ) + sigbuf_boolarray syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply); // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG) // Stops the possibility of dev_mon being high while some other sig is high. @@ -174,17 +180,33 @@ defproc chip_texel (bd in, out; (i:NSMX4: ands_devmon[i].a = syn_mon_dec_x.out[1+i*4]; ands_devmon[i].b = DEV_DEBUG; - ands_devmon[i].y = syn_mon_x[1+i*4]; + ands_devmon[i].y = syn_mon_x_buf.in[1+i*4]; ands_devmon[i].vdd = supply.vdd; ands_devmon[i].vss = supply.vss; ) // Wire up the non-ANDed lines. (i:N_SYN_MON_X: [~(i%4 = 1) -> - syn_mon_x[i] = syn_mon_dec_x.out[i]; + syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i]; ] ) ] + + // Create TBUFs for each synapse column, + // ctrl wired to mon line (0'th in each 4). + pint N_TBUF = N_SYN_X * N_MON_AMZO_PER_SYN; + TBUF_X4 syn_x_AMZI_tbuf[N_TBUF]; + (i:N_SYN_X: + (j:N_MON_AMZO_PER_SYN: + index = i*N_MON_AMZO_PER_SYN + j; + syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index]; + syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4]; + syn_x_AMZI_tbuf[index].y = syn_mon_AMO[j]; + ) + ) + + +