diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index 1e38b09..7a54066 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -54,7 +54,7 @@ defproc buffer_register(avMx1of2 in; Mx1of2 out; bool? out_v, flush, //control -bool _en, _reset_BX,_reset_BXX[N]; +bool _en, _reset_BX[N]; bool _in_aB; bool _reset; @@ -63,11 +63,10 @@ bool _resetX[N]; // Reset sigs INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); sigbuf reset_sb(.in = _reset, .out = _resetX, .supply = supply); -BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd, .vss=supply.vss); -sigbuf resetB_bufarray(.in=_reset_BX, .out=_reset_BXX); +sigbuf resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply); A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, - .pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); + .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss); INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); @@ -77,7 +76,6 @@ INV_X1 flush_inv(.a = flush, .y = _flushB); sigbuf flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); _en = _in_aB; - //validity bool _in_v; vtree vc(.in=in.d,.out=_in_v,.supply=supply); @@ -85,11 +83,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); //function bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; -// bool _en_X_t[N],_en_X_f[N]; A_1C2N_SB_X4 f_buf_func[N]; A_1C2N_RB_X4 t_buf_func[N]; -// sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); -// sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); sigbuf en_buf(.in=_en, .supply=supply); (i:N: f_buf_func[i].y=out.d[i].f; @@ -108,23 +103,21 @@ sigbuf en_buf(.in=_en, .supply=supply); t_buf_func[i].vss=supply.vss; f_buf_func[i].pr = _resetX[i]; f_buf_func[i].sr = _resetX[i]; - t_buf_func[i].pr_B = _reset_BXX[i]; - t_buf_func[i].sr_B = _reset_BXX[i]; + t_buf_func[i].pr_B = _reset_BX[i]; + t_buf_func[i].sr_B = _reset_BX[i]; ) } /** * A single register made out of A cells. - * last bit is whether to read or write. + * MSB is whether to read or write. * Currently only handles writing. */ export template defproc register_acells(avMx1of2 in; Mx1of2 out; bool? reset_B; power supply) { -// BIG TODO -// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET bool _en2; bool _w; @@ -189,65 +182,71 @@ AND2_X1 gandalf_f[N]; * Input packets should be * [-addr-][-word-][r/w] */ -export template -defproc register_w_array(avMx1of2 in; Mx1of2 data[M]; - bool? reset_B; power supply) { -// BIG TODO -// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET -vtree input_valid(.in = in.d, .out = in.v, - .supply = supply); +// UNUSED +// UNUSED +// UNUSED +// UNUSED + +// export template +// defproc register_w_array(avMx1of2 in; Mx1of2 data[M]; +// bool? reset_B; power supply) { + +// // BIG TODO +// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET +// vtree input_valid(.in = in.d, .out = in.v, +// .supply = supply); -// Address decoder -decoder_dualrail decoder(.supply = supply); -(i:NcA: - decoder.in.d[i] = in.d.d[i]; -) +// // Address decoder +// decoder_dualrail decoder(.supply = supply); +// (i:NcA: +// decoder.in.d[i] = in.d.d[i]; +// ) -// OrTree over acks from all registers -ortree ack_ortree(.supply = supply); +// // OrTree over acks from all registers +// ortree ack_ortree(.supply = supply); -// C element handling in ack -A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a, - .vss = supply.vss, .vdd = supply.vdd); +// // C element handling in ack +// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a, +// .vss = supply.vss, .vdd = supply.vdd); -// Write bit selector -bool _w = in.d.d[NcA+NcW].t; -A_2C_B_X1 write_selectors[M]; -(i:M: - write_selectors[i].c1 = _w; - write_selectors[i].c2 = decoder.out[i]; - write_selectors[i].vdd = supply.vdd; - write_selectors[i].vss = supply.vss; -) +// // Write bit selector +// bool _w = in.d.d[NcA+NcW].t; +// A_2C_B_X1 write_selectors[M]; +// (i:M: +// write_selectors[i].c1 = _w; +// write_selectors[i].c2 = decoder.out[i]; +// write_selectors[i].vdd = supply.vdd; +// write_selectors[i].vss = supply.vss; +// ) -// Registers -register_acells registers[M]; -TIELO_X1 tielow_writebit_f[M]; -(i:M: - // Connect each register to word inputs. - (j:NcW: - registers[i].in.d.d[j] = in.d.d[j + NcA]; - ) +// // Registers +// register_acells registers[M]; +// TIELO_X1 tielow_writebit_f[M]; +// (i:M: +// // Connect each register to word inputs. +// (j:NcW: +// registers[i].in.d.d[j] = in.d.d[j + NcA]; +// ) - // Connect the (selected) write bit - registers[i].in.d.d[NcW].t = write_selectors[i].y; - tielow_writebit_f[i].vdd = supply.vdd; - tielow_writebit_f[i].vss = supply.vss; - registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y; +// // Connect the (selected) write bit +// registers[i].in.d.d[NcW].t = write_selectors[i].y; +// tielow_writebit_f[i].vdd = supply.vdd; +// tielow_writebit_f[i].vss = supply.vss; +// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y; - // Connect to ack ortree - registers[i].in.a = ack_ortree.in[i]; +// // Connect to ack ortree +// registers[i].in.a = ack_ortree.in[i]; - // Connect outputs - data[i] = registers[i].out; +// // Connect outputs +// data[i] = registers[i].out; - registers[i].supply = supply; - registers[i].reset_B = reset_B; -) +// registers[i].supply = supply; +// registers[i].reset_B = reset_B; +// ) -} +// } /** * Array of registers made out of A-cells @@ -287,8 +286,9 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ac // Bit to join the acks either from read or write bool _read_ack; _read_ack = out.a; -OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a, +OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .vdd = supply.vdd, .vss = supply.vss); +A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a); // Write bit selector bool _w = in.d.d[NcA+NcW].t;