diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index 5522717..554fda4 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -71,7 +71,7 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
     BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
     sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
     // Creating the different flip flop arrays
-    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
+    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
     andtree<log_nw> atree[_nw];
     AND2_X1 and_encoder[_nw];
     sigbuf<wl> clock_buffer[_nw];
@@ -98,7 +98,16 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
         and_encoder[_word_idx].vss = supply.vss;
         clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
         clock_buffer[_word_idx].supply = supply;
-
+        // Describing all the FF and their connection
+        (_bit_idx:wl:
+            clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
+            // ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
+            // ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
+            // ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
+        )
     )
 }
 }}
diff --git a/test/unit_tests/register_write/run/prsim.out b/test/unit_tests/register_write/run/prsim.out
index d33051a..05b2824 100644
--- a/test/unit_tests/register_write/run/prsim.out
+++ b/test/unit_tests/register_write/run/prsim.out
@@ -1,4 +1,4 @@
-t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.clk_dly.and2[0]._y t.in.d.d[0].t t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.clock_buffer[2].out[0] t.registers.val_input.ct.in[1] t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.clock_buffer[5].out[0] t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.registers.atree[2].in[1] t.dly_cfg[0] t.registers.ff[4].__clk t.registers._in_v_temp t.registers.atree[1].in[0] t.registers._out_encoder[2] t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.val_input.ct.in[0] t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.in.v t.registers._clock_word_temp[5] t.registers.clock_buffer[0].out[0] t.registers.clock_buffer[4].out[0] t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.in.d.d[4].t t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers._clock_word_temp[3] t.registers._out_encoder[7] t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers._out_encoder[4] t.registers.val_input.ct.in[3] t.registers.ff[7]._mqi t.registers._out_encoder[5] t.registers.ff[5].q t.in.d.d[1].t t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers._clock_word_temp[4] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ack_dly.dly[2].___y t.registers._clock_word_temp[7] t.registers.clock_buffer[6].out[0] t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers._clock_word_temp[6] t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.atree[0].in[1] t.registers.clk_dly._a[1] t.registers.val_input.ct.in[4] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.val_input.OR2_tf[3]._y t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.clk_dly.dly[0].___y t.registers.ff[8].q t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers._out_encoder[6] t.registers.ff[6].reset_B t.registers.clock_buffer[4].buf1._y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.clk_dly.dly[0]._y t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.ff[14].q t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.atree[6].and2s[0]._y t.registers.atree[0].and2s[0]._y t.registers.clock_buffer[3].out[0] t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.clock_buffer[2].buf1._y t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.clk_dly.dly[0].y t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.clock_buffer[7].out[0] t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.atree[7].and2s[0]._y t.registers.ff[4]._clk t.registers.clock_buffer[3].buf1._y t.registers.clock_buffer[1].out[0] t.registers.val_input.ct.tmp[5] t.registers.ff[12]._mqi t.registers.atree[4].and2s[0]._y t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.and_encoder[0]._y t.registers.ff[13]._mqi t.registers.and_encoder[6]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ff[8].reset_B t.registers.and_encoder[5]._y t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.atree[3].and2s[0]._y t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.atree[2].and2s[0]._y t.registers.ff[11]._sqib t.registers.clock_buffer[7].buf1._y t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.clock_buffer[5].buf1._y t.registers.val_input_X.buf1._y t.registers.ff[11].q t.registers.and_encoder[7]._y t.registers.val_input.OR2_tf[0]._y t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.clock_buffer[6].buf1._y t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.atree[5].and2s[0]._y t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.and_encoder[1]._y t.registers.and_encoder[4]._y t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.val_input.OR2_tf[4]._y t.registers.ff[11].d t.registers.val_input.ct.C2Els[0]._y t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.val_input.ct.C3Els[0]._y t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B 
+t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.clk_dly.and2[0]._y t.in.d.d[0].t t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers._clock_buffer_out[0] t.registers.val_input.ct.in[1] t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.registers.atree[2].in[1] t.dly_cfg[0] t.registers.ff[4].__clk t.registers._in_v_temp t.registers.atree[1].in[0] t.registers._out_encoder[2] t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.val_input.ct.in[0] t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.in.v t.registers._clock_word_temp[5] t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.in.d.d[4].t t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers._clock_word_temp[3] t.registers._out_encoder[7] t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers._out_encoder[4] t.registers.val_input.ct.in[3] t.registers.ff[7]._mqi t.registers._out_encoder[5] t.registers.ff[5].q t.in.d.d[1].t t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers._clock_word_temp[4] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ack_dly.dly[2].___y t.registers._clock_word_temp[7] t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers._clock_word_temp[6] t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.atree[0].in[1] t.registers.clk_dly._a[1] t.registers.val_input.ct.in[4] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.val_input.OR2_tf[3]._y t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.clk_dly.dly[0].___y t.registers.ff[8].q t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers._out_encoder[6] t.registers.ff[6].reset_B t.registers.clock_buffer[4].buf1._y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.clk_dly.dly[0]._y t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.ff[14].q t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.atree[6].and2s[0]._y t.registers.atree[0].and2s[0]._y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.clock_buffer[2].buf1._y t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.clk_dly.dly[0].y t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.atree[7].and2s[0]._y t.registers.ff[4]._clk t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ff[12]._mqi t.registers.atree[4].and2s[0]._y t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.and_encoder[0]._y t.registers.ff[13]._mqi t.registers.and_encoder[6]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ff[8].reset_B t.registers.and_encoder[5]._y t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.atree[3].and2s[0]._y t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.atree[2].and2s[0]._y t.registers.ff[11]._sqib t.registers.clock_buffer[7].buf1._y t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.clock_buffer[5].buf1._y t.registers.val_input_X.buf1._y t.registers.ff[11].q t.registers.and_encoder[7]._y t.registers.val_input.OR2_tf[0]._y t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.clock_buffer[6].buf1._y t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.atree[5].and2s[0]._y t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.and_encoder[1]._y t.registers.and_encoder[4]._y t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.val_input.OR2_tf[4]._y t.registers.ff[11].d t.registers.val_input.ct.C2Els[0]._y t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.val_input.ct.C3Els[0]._y t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B 
 [0] start test
 	     16472 t.in.d.d[0].f : 0
 	     16472 t.data[1].d[1] : 0
@@ -38,265 +38,261 @@ t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t
 	     31306 t.registers._out_encoder[7] : 0  [by t.registers.atree[7].and2s[0]._y:=1]
 	     31309 t.registers.and_encoder[7]._y : 1  [by t.registers._out_encoder[7]:=0]
 	     31465 t.registers.clock_buffer[3].buf1._y : 1  [by t.registers._clock_word_temp[3]:=0]
-	     32016 t.registers.clock_buffer[3].out[0] : 0  [by t.registers.clock_buffer[3].buf1._y:=1]
 	     41699 t.registers._out_encoder[1] : 0  [by t.registers.atree[1].and2s[0]._y:=1]
+	     42250 t.registers.and_encoder[1]._y : 1  [by t.registers._out_encoder[1]:=0]
 	     42740 t.registers._clock_word_temp[5] : 0  [by t.registers.and_encoder[5]._y:=1]
-	     42770 t.registers.and_encoder[1]._y : 1  [by t.registers._out_encoder[1]:=0]
+	     43321 t.registers._clock_word_temp[1] : 0  [by t.registers.and_encoder[1]._y:=1]
 	     43694 t.registers.clock_buffer[5].buf1._y : 1  [by t.registers._clock_word_temp[5]:=0]
-	     43851 t.registers._clock_word_temp[1] : 0  [by t.registers.and_encoder[1]._y:=1]
-	     44833 t.registers.clock_buffer[1].buf1._y : 1  [by t.registers._clock_word_temp[1]:=0]
-	     44851 t.registers.clock_buffer[1].out[0] : 0  [by t.registers.clock_buffer[1].buf1._y:=1]
+	     44402 t.registers.clock_buffer[1].buf1._y : 1  [by t.registers._clock_word_temp[1]:=0]
 	     46299 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
 	     53437 t.registers._clock_word_temp[6] : 0  [by t.registers.and_encoder[6]._y:=1]
 	     53750 t.registers._clock_word_temp[7] : 0  [by t.registers.and_encoder[7]._y:=1]
-	     57450 t.registers.clock_buffer[6].buf1._y : 1  [by t.registers._clock_word_temp[6]:=0]
-	     57753 t.registers.clock_buffer[7].buf1._y : 1  [by t.registers._clock_word_temp[7]:=0]
+	     54732 t.registers.clock_buffer[7].buf1._y : 1  [by t.registers._clock_word_temp[7]:=0]
 	     59740 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
+	     59758 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
 	     60570 t.registers.val_input.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
-	     61072 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
-	     61275 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[1]:=0]
-	     63129 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
-	     64500 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
-	     64639 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	     63771 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	     64573 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
 	     67334 t.registers.and_encoder[2]._y : 1  [by t.registers._out_encoder[2]:=0]
-	     67403 t.registers._clock_word_temp[2] : 0  [by t.registers.and_encoder[2]._y:=1]
-	     67414 t.registers.clock_buffer[2].buf1._y : 1  [by t.registers._clock_word_temp[2]:=0]
 	     68165 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
-	     68369 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
-	     68384 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
-	     68385 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
-	     68422 t.registers.clock_buffer[0].out[0] : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
-	     79337 t.registers.clock_buffer[7].out[0] : 0  [by t.registers.clock_buffer[7].buf1._y:=1]
+	     68667 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
+	     68870 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
+	     70724 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
+	     72094 t.registers._clock_word_temp[2] : 0  [by t.registers.and_encoder[2]._y:=1]
+	     72233 t.registers.clock_buffer[2].buf1._y : 1  [by t.registers._clock_word_temp[2]:=0]
 	     81838 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
-	     82577 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
-	     82689 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
-	     98164 t.registers.clock_buffer[5].out[0] : 0  [by t.registers.clock_buffer[5].buf1._y:=1]
-	    100985 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
-	    101025 t.registers.clock_buffer[4].out[0] : 0  [by t.registers.clock_buffer[4].buf1._y:=1]
-	    102351 t.registers.clock_buffer[6].out[0] : 0  [by t.registers.clock_buffer[6].buf1._y:=1]
-	    119200 t.registers.clock_buffer[2].out[0] : 0  [by t.registers.clock_buffer[2].buf1._y:=1]
-	    130201 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
-	    130458 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
-	    130545 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
-	    130546 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
-	    130839 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
-	    132352 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
-	    132846 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
-	    134055 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
-	    134645 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
-	    134823 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
-	    135626 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+	     86157 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[1]:=0]
+	     86226 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	    107907 t.registers.clock_buffer[6].buf1._y : 1  [by t.registers._clock_word_temp[6]:=0]
+	    108672 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
+	    108683 t.registers._clock_buffer_out[0] : 0  [by t.registers.clock_buffer[4].buf1._y:=1]
+	    118184 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	    169970 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
+	    170174 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	    170189 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
+	    170190 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	    170227 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    170339 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    170929 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	    170969 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	    217851 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    218108 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    218195 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    218489 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
 t.registers.ff[4].q t.registers.ff[15].reset_B t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.dly_cfg[0] t.registers.ff[4].__clk t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers.clk_dly.and2[1]._y t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers.ff[7]._mqi t.registers.ff[5].q t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers.ack_dly.dly[2].___y t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers.ack_dly.mu2[0]._y t.registers.clk_dly._a[1] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.ff[8].q t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers.ff[6].reset_B t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.ff[14].q t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.ff[4]._clk t.registers.ff[12]._mqi t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.ff[13]._mqi t.registers.ff[8].reset_B t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.ff[11]._sqib t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.ff[11].q t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.ff[11].d t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B 
-	    135626 Reset : 0
-	    135790 t._reset_B : 1  [by Reset:=0]
-	    135812 t.registers.reset_buf_BXX._y : 0  [by t._reset_B:=1]
-	    136659 t.registers._reset_mem_BX : 1  [by t.registers.reset_buf_BXX._y:=0]
-	    137985 t.registers.reset_buf_BX._y : 0  [by t._reset_B:=1]
-	    138118 t.registers._reset_BX : 1  [by t.registers.reset_buf_BX._y:=0]
-	    166787 t.registers.reset_bufarray.buf6._y : 0  [by t.registers._reset_mem_BX:=1]
-	    182449 t.registers._reset_mem_BXX[0] : 1  [by t.registers.reset_bufarray.buf6._y:=0]
+	    218489 Reset : 0
+	    218490 t._reset_B : 1  [by Reset:=0]
+	    220296 t.registers.reset_buf_BX._y : 0  [by t._reset_B:=1]
+	    220497 t.registers.reset_buf_BXX._y : 0  [by t._reset_B:=1]
+	    221087 t.registers._reset_mem_BX : 1  [by t.registers.reset_buf_BXX._y:=0]
+	    221265 t.registers.reset_bufarray.buf6._y : 0  [by t.registers._reset_mem_BX:=1]
+	    221505 t.registers._reset_BX : 1  [by t.registers.reset_buf_BX._y:=0]
+	    222068 t.registers._reset_mem_BXX[0] : 1  [by t.registers.reset_bufarray.buf6._y:=0]
 [1] reset completed
-	    182449 t.dly_cfg[0] : 1
-	    182449 t.dly_cfg[1] : 1
-	    182456 t.registers.clk_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
-	    182670 t.registers.ack_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
-	    182808 t.registers.ack_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
-	    196565 t.registers.clk_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
-	    196595 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.mu2[0]._s:=0]
-	    203308 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
-	    260769 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
-	    260860 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
-	    263049 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
-	    263056 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
-	    265843 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
-	    265949 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
-	    266027 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
-	    266302 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
-	    285298 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
-	    285753 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
-	    285765 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
-	    286169 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
-	    286181 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
-	    292097 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
-	    296373 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
-	    299272 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
-	    303567 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
-	    303569 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
-	    308104 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
-	    309353 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
-	    312852 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
-	    313018 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
-	    313093 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
-	    313438 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
-	    313576 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
-	    318839 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
-	    318841 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
-	    362758 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
-	    362759 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
-	    363307 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
-	    363318 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
-	    363688 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
-	    363755 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
-	    366396 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
-	    366412 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
-	    370974 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+	    222068 t.dly_cfg[0] : 1
+	    222068 t.dly_cfg[1] : 1
+	    222090 t.registers.ack_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    222232 t.registers.ack_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    222915 t.registers.clk_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    224263 t.registers.clk_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    254391 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.mu2[0]._s:=0]
+	    254524 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    270186 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    270545 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    284661 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    284882 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    284889 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    284919 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    291632 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    349093 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    349184 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    351373 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    351380 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    354167 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    354273 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    354351 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    354626 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    373622 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    374077 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    374089 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    374493 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    374505 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    380421 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    384697 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    387596 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    391891 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    391893 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    396428 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    397677 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    401176 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	    401342 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	    401417 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	    401762 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	    401900 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	    407163 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	    407165 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	    451082 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	    451083 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
 [2] delay line set
-	    370974 t.in.d.d[0].t : 1
-	    370974 t.in.d.d[4].f : 1
-	    370974 t.registers.atree[0].in[0] : 1
-	    370974 t.in.d.d[1].t : 1
-	    370974 t.registers.atree[0].in[1] : 1
-	    370976 t.registers.atree[0].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
-	    370979 t.registers._out_encoder[0] : 1  [by t.registers.atree[0].and2s[0]._y:=0]
-	    371502 t.registers.val_input.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
-	    371531 t.registers.val_input.ct.in[0] : 1  [by t.registers.val_input.OR2_tf[0]._y:=0]
-	    373409 t.registers.val_input.OR2_tf[4]._y : 0  [by t.in.d.d[4].f:=1]
-	    373726 t.registers.val_input.ct.in[4] : 1  [by t.registers.val_input.OR2_tf[4]._y:=0]
-	    384015 t.registers.val_input.OR2_tf[3]._y : 0  [by t.registers.atree[0].in[1]:=1]
-	    385616 t.registers.val_input.ct.in[3] : 1  [by t.registers.val_input.OR2_tf[3]._y:=0]
-	    394899 t.registers.val_input.OR2_tf[1]._y : 0  [by t.in.d.d[1].t:=1]
-	    395052 t.registers.val_input.ct.in[1] : 1  [by t.registers.val_input.OR2_tf[1]._y:=0]
-	    395096 t.registers.val_input.ct.C2Els[0]._y : 0  [by t.registers.val_input.ct.in[1]:=1]
-	    397854 t.registers.val_input.OR2_tf[2]._y : 0  [by t.registers.atree[0].in[0]:=1]
-	    397857 t.registers.val_input.ct.tmp[5] : 1  [by t.registers.val_input.ct.C2Els[0]._y:=0]
-	    411537 t.registers.val_input.ct.in[2] : 1  [by t.registers.val_input.OR2_tf[2]._y:=0]
-	    411538 t.registers.val_input.ct.C3Els[0]._y : 0  [by t.registers.val_input.ct.in[2]:=1]
-	    411755 t.registers.val_input.ct.tmp[6] : 1  [by t.registers.val_input.ct.C3Els[0]._y:=0]
-	    411777 t.registers.val_input.ct.C2Els[1]._y : 0  [by t.registers.val_input.ct.tmp[6]:=1]
-	    411778 t.registers._in_v_temp : 1  [by t.registers.val_input.ct.C2Els[1]._y:=0]
-	    413359 t.registers.clk_dly.and2[0]._y : 0  [by t.registers._in_v_temp:=1]
-	    413518 t.registers.clk_dly.dly[0].a : 1  [by t.registers.clk_dly.and2[0]._y:=0]
-	    421123 t.registers.val_input_X.buf1._y : 0  [by t.registers._in_v_temp:=1]
-	    422410 t.in.v : 1  [by t.registers.val_input_X.buf1._y:=0]
-	    431932 t.registers.atree[4].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
-	    433194 t.registers.clk_dly.dly[0]._y : 0  [by t.registers.clk_dly.dly[0].a:=1]
-	    433339 t.registers.clk_dly.dly[0].__y : 1  [by t.registers.clk_dly.dly[0]._y:=0]
-	    434164 t.registers._out_encoder[4] : 1  [by t.registers.atree[4].and2s[0]._y:=0]
-	    436171 t.registers.clk_dly.dly[0].___y : 0  [by t.registers.clk_dly.dly[0].__y:=1]
-	    442525 t.registers.clk_dly.dly[0].y : 1  [by t.registers.clk_dly.dly[0].___y:=0]
-	    442526 t.registers.clk_dly.mu2[0]._y : 0  [by t.registers.clk_dly.dly[0].y:=1]
-	    481810 t.registers.clk_dly._a[1] : 1  [by t.registers.clk_dly.mu2[0]._y:=0]
-	    481972 t.registers.clk_dly.and2[1]._y : 0  [by t.registers.clk_dly._a[1]:=1]
-	    489341 t.registers.clk_dly.dly[1].a : 1  [by t.registers.clk_dly.and2[1]._y:=0]
-	    489355 t.registers.clk_dly.dly[1]._y : 0  [by t.registers.clk_dly.dly[1].a:=1]
-	    489362 t.registers.clk_dly.dly[1].__y : 1  [by t.registers.clk_dly.dly[1]._y:=0]
-	    489522 t.registers.clk_dly.dly[1].___y : 0  [by t.registers.clk_dly.dly[1].__y:=1]
-	    511079 t.registers.clk_dly.dly[1].y : 1  [by t.registers.clk_dly.dly[1].___y:=0]
-	    511080 t.registers.clk_dly.dly[2]._y : 0  [by t.registers.clk_dly.dly[1].y:=1]
-	    511081 t.registers.clk_dly.dly[2].__y : 1  [by t.registers.clk_dly.dly[2]._y:=0]
-	    511082 t.registers.clk_dly.dly[2].___y : 0  [by t.registers.clk_dly.dly[2].__y:=1]
-	    513325 t.registers.clk_dly.dly[2].y : 1  [by t.registers.clk_dly.dly[2].___y:=0]
-	    513512 t.registers.clk_dly.mu2[1]._y : 0  [by t.registers.clk_dly.dly[2].y:=1]
-	    513513 t.registers._clock_temp : 1  [by t.registers.clk_dly.mu2[1]._y:=0]
-	    517695 t.registers.clk_X.buf1._y : 0  [by t.registers._clock_temp:=1]
-	    552477 t.registers._clock : 1  [by t.registers.clk_X.buf1._y:=0]
-	    552478 t.registers.and_encoder[4]._y : 0  [by t.registers._clock:=1]
-	    552482 t.registers.ack_dly.and2[0]._y : 0  [by t.registers._clock:=1]
-	    552483 t.registers.ack_dly.dly[0].a : 1  [by t.registers.ack_dly.and2[0]._y:=0]
-	    552500 t.registers.ack_dly.dly[0]._y : 0  [by t.registers.ack_dly.dly[0].a:=1]
-	    553330 t.registers.and_encoder[0]._y : 0  [by t.registers._clock:=1]
-	    553369 t.registers._clock_word_temp[4] : 1  [by t.registers.and_encoder[4]._y:=0]
-	    553372 t.registers.clock_buffer[4].buf1._y : 0  [by t.registers._clock_word_temp[4]:=1]
-	    554313 t.registers.clock_buffer[4].out[0] : 1  [by t.registers.clock_buffer[4].buf1._y:=0]
-	    555073 t.registers.ack_dly.dly[0].__y : 1  [by t.registers.ack_dly.dly[0]._y:=0]
-	    561691 t.registers._clock_word_temp[0] : 1  [by t.registers.and_encoder[0]._y:=0]
-	    561692 t.registers.clock_buffer[0].buf1._y : 0  [by t.registers._clock_word_temp[0]:=1]
-	    561734 t.registers.clock_buffer[0].out[0] : 1  [by t.registers.clock_buffer[0].buf1._y:=0]
-	    614035 t.registers.ack_dly.dly[0].___y : 0  [by t.registers.ack_dly.dly[0].__y:=1]
-	    616852 t.registers.ack_dly.dly[0].y : 1  [by t.registers.ack_dly.dly[0].___y:=0]
-	    630585 t.registers.ack_dly.mu2[0]._y : 0  [by t.registers.ack_dly.dly[0].y:=1]
-	    630680 t.registers.ack_dly._a[1] : 1  [by t.registers.ack_dly.mu2[0]._y:=0]
-	    631015 t.registers.ack_dly.and2[1]._y : 0  [by t.registers.ack_dly._a[1]:=1]
-	    631023 t.registers.ack_dly.dly[1].a : 1  [by t.registers.ack_dly.and2[1]._y:=0]
-	    631057 t.registers.ack_dly.dly[1]._y : 0  [by t.registers.ack_dly.dly[1].a:=1]
-	    644944 t.registers.ack_dly.dly[1].__y : 1  [by t.registers.ack_dly.dly[1]._y:=0]
-	    645862 t.registers.ack_dly.dly[1].___y : 0  [by t.registers.ack_dly.dly[1].__y:=1]
-	    645866 t.registers.ack_dly.dly[1].y : 1  [by t.registers.ack_dly.dly[1].___y:=0]
-	    692244 t.registers.ack_dly.dly[2]._y : 0  [by t.registers.ack_dly.dly[1].y:=1]
-	    694642 t.registers.ack_dly.dly[2].__y : 1  [by t.registers.ack_dly.dly[2]._y:=0]
-	    697857 t.registers.ack_dly.dly[2].___y : 0  [by t.registers.ack_dly.dly[2].__y:=1]
-	    744976 t.registers.ack_dly.dly[2].y : 1  [by t.registers.ack_dly.dly[2].___y:=0]
-	    745024 t.registers.ack_dly.mu2[1]._y : 0  [by t.registers.ack_dly.dly[2].y:=1]
-	    745027 t.registers._in_a_temp : 1  [by t.registers.ack_dly.mu2[1]._y:=0]
-	    745205 t.registers.ack_input_X.buf1._y : 0  [by t.registers._in_a_temp:=1]
-	    766182 t.in.a : 1  [by t.registers.ack_input_X.buf1._y:=0]
-	    766182 t.in.d.d[0].t : 0
-	    766182 t.in.d.d[4].f : 0
-	    766182 t.registers.atree[0].in[0] : 0
-	    766182 t.in.d.d[1].t : 0
-	    766182 t.registers.atree[0].in[1] : 0
-	    766183 t.registers.val_input.OR2_tf[3]._y : 1  [by t.registers.atree[0].in[1]:=0]
-	    766256 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
-	    766355 t.registers.atree[4].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
-	    766359 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
-	    766366 t.registers.val_input.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
-	    766462 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
-	    767009 t.registers.atree[0].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
-	    767145 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
-	    767146 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
-	    772133 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
-	    772374 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
-	    778081 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
-	    782040 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
-	    782052 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[0]:=0]
-	    785952 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
-	    786192 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
-	    787221 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
-	    787222 t.registers.clock_buffer[0].out[0] : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
-	    803647 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
-	    803703 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
-	    805667 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[0]:=0]
-	    805668 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
-	    805705 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[2]:=0]
-	    829080 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
-	    829081 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
-	    832645 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
-	    832658 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
-	    834337 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
-	    834694 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
-	    834719 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
-	    834740 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
-	    834741 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
-	    844389 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
-	    844390 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.dly[0].y:=0]
-	    844391 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
-	    844552 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
-	    845589 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
-	    845594 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
-	    846175 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
-	    846583 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
-	    846594 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
-	    847641 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
-	    847655 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
-	    847673 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
-	    847677 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
-	    847781 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
-	    848709 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
-	    849642 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
-	    849913 t.registers.clock_buffer[4].out[0] : 0  [by t.registers.clock_buffer[4].buf1._y:=1]
-	    879225 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
-	    887680 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
-	    887908 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
-	    888751 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
-	    890210 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
-	    890280 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
-	    940702 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
-	    940713 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
-	    940716 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
-	    940770 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
-	    941918 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
-	    943079 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
-	    951731 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
-	    951812 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
-	    962889 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
-	    980872 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
-	    980964 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
-	    989275 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
-	    991019 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
-	    991632 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
-	   1005654 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
-	   1005699 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
-	   1006696 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
-	   1008345 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
-	   1008870 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+	    451083 t.in.d.d[0].t : 1
+	    451083 t.in.d.d[4].f : 1
+	    451083 t.registers.atree[0].in[0] : 1
+	    451083 t.in.d.d[1].t : 1
+	    451083 t.registers.atree[0].in[1] : 1
+	    451094 t.registers.val_input.OR2_tf[4]._y : 0  [by t.in.d.d[4].f:=1]
+	    451099 t.registers.atree[0].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    451150 t.registers.val_input.OR2_tf[1]._y : 0  [by t.in.d.d[1].t:=1]
+	    451453 t.registers.val_input.OR2_tf[2]._y : 0  [by t.registers.atree[0].in[0]:=1]
+	    451622 t.registers.val_input.ct.in[4] : 1  [by t.registers.val_input.OR2_tf[4]._y:=0]
+	    451631 t.registers.val_input.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
+	    453534 t.registers._out_encoder[0] : 1  [by t.registers.atree[0].and2s[0]._y:=0]
+	    453724 t.registers.val_input.OR2_tf[3]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    453726 t.registers.val_input.ct.in[3] : 1  [by t.registers.val_input.OR2_tf[3]._y:=0]
+	    455645 t.registers.atree[4].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    464672 t.registers.val_input.ct.in[0] : 1  [by t.registers.val_input.OR2_tf[0]._y:=0]
+	    475378 t.registers.val_input.ct.in[2] : 1  [by t.registers.val_input.OR2_tf[2]._y:=0]
+	    475381 t.registers.val_input.ct.C3Els[0]._y : 0  [by t.registers.val_input.ct.in[2]:=1]
+	    475410 t.registers.val_input.ct.tmp[6] : 1  [by t.registers.val_input.ct.C3Els[0]._y:=0]
+	    478030 t.registers.val_input.ct.in[1] : 1  [by t.registers.val_input.OR2_tf[1]._y:=0]
+	    478347 t.registers.val_input.ct.C2Els[0]._y : 0  [by t.registers.val_input.ct.in[1]:=1]
+	    479948 t.registers.val_input.ct.tmp[5] : 1  [by t.registers.val_input.ct.C2Els[0]._y:=0]
+	    480101 t.registers.val_input.ct.C2Els[1]._y : 0  [by t.registers.val_input.ct.tmp[5]:=1]
+	    480145 t.registers._in_v_temp : 1  [by t.registers.val_input.ct.C2Els[1]._y:=0]
+	    482906 t.registers.clk_dly.and2[0]._y : 0  [by t.registers._in_v_temp:=1]
+	    482907 t.registers.clk_dly.dly[0].a : 1  [by t.registers.clk_dly.and2[0]._y:=0]
+	    483124 t.registers.clk_dly.dly[0]._y : 0  [by t.registers.clk_dly.dly[0].a:=1]
+	    483146 t.registers.clk_dly.dly[0].__y : 1  [by t.registers.clk_dly.dly[0]._y:=0]
+	    483147 t.registers.clk_dly.dly[0].___y : 0  [by t.registers.clk_dly.dly[0].__y:=1]
+	    484728 t.registers.clk_dly.dly[0].y : 1  [by t.registers.clk_dly.dly[0].___y:=0]
+	    493828 t.registers.val_input_X.buf1._y : 0  [by t.registers._in_v_temp:=1]
+	    493987 t.in.v : 1  [by t.registers.val_input_X.buf1._y:=0]
+	    494073 t.registers.clk_dly.mu2[0]._y : 0  [by t.registers.clk_dly.dly[0].y:=1]
+	    513749 t.registers.clk_dly._a[1] : 1  [by t.registers.clk_dly.mu2[0]._y:=0]
+	    515036 t.registers.clk_dly.and2[1]._y : 0  [by t.registers.clk_dly._a[1]:=1]
+	    516603 t.registers._out_encoder[4] : 1  [by t.registers.atree[4].and2s[0]._y:=0]
+	    517268 t.registers.clk_dly.dly[1].a : 1  [by t.registers.clk_dly.and2[1]._y:=0]
+	    517413 t.registers.clk_dly.dly[1]._y : 0  [by t.registers.clk_dly.dly[1].a:=1]
+	    520245 t.registers.clk_dly.dly[1].__y : 1  [by t.registers.clk_dly.dly[1]._y:=0]
+	    526599 t.registers.clk_dly.dly[1].___y : 0  [by t.registers.clk_dly.dly[1].__y:=1]
+	    526600 t.registers.clk_dly.dly[1].y : 1  [by t.registers.clk_dly.dly[1].___y:=0]
+	    565884 t.registers.clk_dly.dly[2]._y : 0  [by t.registers.clk_dly.dly[1].y:=1]
+	    566046 t.registers.clk_dly.dly[2].__y : 1  [by t.registers.clk_dly.dly[2]._y:=0]
+	    573415 t.registers.clk_dly.dly[2].___y : 0  [by t.registers.clk_dly.dly[2].__y:=1]
+	    573429 t.registers.clk_dly.dly[2].y : 1  [by t.registers.clk_dly.dly[2].___y:=0]
+	    573436 t.registers.clk_dly.mu2[1]._y : 0  [by t.registers.clk_dly.dly[2].y:=1]
+	    573596 t.registers._clock_temp : 1  [by t.registers.clk_dly.mu2[1]._y:=0]
+	    595153 t.registers.clk_X.buf1._y : 0  [by t.registers._clock_temp:=1]
+	    595154 t.registers._clock : 1  [by t.registers.clk_X.buf1._y:=0]
+	    595155 t.registers.and_encoder[4]._y : 0  [by t.registers._clock:=1]
+	    595155 t.registers.and_encoder[0]._y : 0  [by t.registers._clock:=1]
+	    595156 t.registers._clock_word_temp[0] : 1  [by t.registers.and_encoder[0]._y:=0]
+	    595342 t.registers._clock_word_temp[4] : 1  [by t.registers.and_encoder[4]._y:=0]
+	    597397 t.registers.ack_dly.and2[0]._y : 0  [by t.registers._clock:=1]
+	    597398 t.registers.ack_dly.dly[0].a : 1  [by t.registers.ack_dly.and2[0]._y:=0]
+	    598251 t.registers.ack_dly.dly[0]._y : 0  [by t.registers.ack_dly.dly[0].a:=1]
+	    598256 t.registers.ack_dly.dly[0].__y : 1  [by t.registers.ack_dly.dly[0]._y:=0]
+	    599147 t.registers.ack_dly.dly[0].___y : 0  [by t.registers.ack_dly.dly[0].__y:=1]
+	    599148 t.registers.ack_dly.dly[0].y : 1  [by t.registers.ack_dly.dly[0].___y:=0]
+	    599165 t.registers.ack_dly.mu2[0]._y : 0  [by t.registers.ack_dly.dly[0].y:=1]
+WARNING: interference `t.registers._clock_buffer_out[0]'
+>> cause: t.registers.clock_buffer[0].buf1._y (val: 0)
+>> time:     599338
+	    599338 t.registers.clock_buffer[0].buf1._y : 0  [by t.registers._clock_word_temp[0]:=1]
+	    601738 t.registers.ack_dly._a[1] : 1  [by t.registers.ack_dly.mu2[0]._y:=0]
+	    601741 t.registers.ack_dly.and2[1]._y : 0  [by t.registers.ack_dly._a[1]:=1]
+	    602682 t.registers.ack_dly.dly[1].a : 1  [by t.registers.ack_dly.and2[1]._y:=0]
+	    607699 t.registers._clock_buffer_out[0] : X  [by t.registers.clock_buffer[0].buf1._y:=0]
+	    630124 t.registers.clock_buffer[4].buf1._y : 0  [by t.registers._clock_word_temp[4]:=1]
+	    661644 t.registers.ack_dly.dly[1]._y : 0  [by t.registers.ack_dly.dly[1].a:=1]
+	    661645 t.registers.ack_dly.dly[1].__y : 1  [by t.registers.ack_dly.dly[1]._y:=0]
+	    661687 t.registers.ack_dly.dly[1].___y : 0  [by t.registers.ack_dly.dly[1].__y:=1]
+	    664504 t.registers.ack_dly.dly[1].y : 1  [by t.registers.ack_dly.dly[1].___y:=0]
+	    678237 t.registers.ack_dly.dly[2]._y : 0  [by t.registers.ack_dly.dly[1].y:=1]
+	    678332 t.registers.ack_dly.dly[2].__y : 1  [by t.registers.ack_dly.dly[2]._y:=0]
+	    678667 t.registers.ack_dly.dly[2].___y : 0  [by t.registers.ack_dly.dly[2].__y:=1]
+	    678675 t.registers.ack_dly.dly[2].y : 1  [by t.registers.ack_dly.dly[2].___y:=0]
+	    678709 t.registers.ack_dly.mu2[1]._y : 0  [by t.registers.ack_dly.dly[2].y:=1]
+	    692596 t.registers._in_a_temp : 1  [by t.registers.ack_dly.mu2[1]._y:=0]
+	    693514 t.registers.ack_input_X.buf1._y : 0  [by t.registers._in_a_temp:=1]
+	    693518 t.in.a : 1  [by t.registers.ack_input_X.buf1._y:=0]
+	    693518 t.in.d.d[0].t : 0
+	    693518 t.in.d.d[4].f : 0
+	    693518 t.registers.atree[0].in[0] : 0
+	    693518 t.in.d.d[1].t : 0
+	    693518 t.registers.atree[0].in[1] : 0
+	    693521 t.registers.val_input.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
+	    693566 t.registers.atree[4].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    693696 t.registers.val_input.OR2_tf[3]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	    695916 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
+	    696733 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    697560 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
+	    699647 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
+	    705465 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
+	    705638 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
+	    705822 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	    705823 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
+	    714498 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
+	    735401 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	    735474 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
+	    735478 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	    739896 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
+	    740637 t.registers.atree[0].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    740733 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
+	    740869 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
+	    740870 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
+	    759916 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
+	    760157 t.registers._clock_buffer_out[0] : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
+	    777184 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
+	    781143 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[0]:=0]
+	    781155 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	    785055 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[5]:=0]
+	    786084 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	    786085 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    786140 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	    786141 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	    831091 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    831128 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    854503 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    854504 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    858068 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+	    859760 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.dly[0].y:=0]
+	    859773 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    876757 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    877114 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    877139 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    877160 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    877161 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    886809 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    886810 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    886811 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    886972 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    888009 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    888014 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    888595 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    889003 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    889014 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    890061 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    890075 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    890093 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    890097 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    890201 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    921645 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    922849 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    931304 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    931532 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    932375 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    933834 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    933904 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    984326 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    984337 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	    984340 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	    984394 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	    985542 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	    986703 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	    995355 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	    995436 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	   1006513 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	   1024496 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+WRONG ASSERT:	"t.registers.ff[0].q" has value X and not 1.
+WRONG ASSERT:	"t.registers.ff[1].q" has value X and not 1.
 [3] clock checked
diff --git a/test/unit_tests/register_write/run/test.prs b/test/unit_tests/register_write/run/test.prs
index 780451f..b663a6e 100644
--- a/test/unit_tests/register_write/run/test.prs
+++ b/test/unit_tests/register_write/run/test.prs
@@ -282,7 +282,6 @@
 = "t.registers.clk_X.supply.vdd" "t.registers.clk_X.buf1.vdd"
 = "t.registers.clk_X.supply.vss" "t.registers.clk_X.buf1.vss"
 = "t.registers.clk_X.out" "t.registers.clk_X.buf1.y"
-= "t.registers.clk_X.out" "t.registers.clk_X._out"
 = "t.registers.clk_X.in" "t.registers.clk_X.buf1.a"
 = "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
 = "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
@@ -659,7 +658,6 @@
 = "t.registers.val_input_X.supply.vdd" "t.registers.val_input_X.buf1.vdd"
 = "t.registers.val_input_X.supply.vss" "t.registers.val_input_X.buf1.vss"
 = "t.registers.val_input_X.out" "t.registers.val_input_X.buf1.y"
-= "t.registers.val_input_X.out" "t.registers.val_input_X._out"
 = "t.registers.val_input_X.in" "t.registers.val_input_X.buf1.a"
 "t.registers.ack_input_X.buf1.a"->"t.registers.ack_input_X.buf1._y"-
 ~("t.registers.ack_input_X.buf1.a")->"t.registers.ack_input_X.buf1._y"+
@@ -668,8 +666,31 @@
 = "t.registers.ack_input_X.supply.vdd" "t.registers.ack_input_X.buf1.vdd"
 = "t.registers.ack_input_X.supply.vss" "t.registers.ack_input_X.buf1.vss"
 = "t.registers.ack_input_X.out" "t.registers.ack_input_X.buf1.y"
-= "t.registers.ack_input_X.out" "t.registers.ack_input_X._out"
 = "t.registers.ack_input_X.in" "t.registers.ack_input_X.buf1.a"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[8]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[7]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[6]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[5]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[4]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[3]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[2]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[0]"
 ~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+
 "t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"-
 "t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"-
@@ -957,9 +978,6 @@
 = "t.registers.atree[7].in[1]" "t.registers.atree[7].tmp[1]"
 = "t.registers.atree[7].out" "t.registers.atree[7].and2s[0].y"
 = "t.registers.atree[7].out" "t.registers.atree[7].tmp[2]"
-= "t.registers._in_v_temp" "t.registers.clk_dly.in"
-= "t.registers._in_v_temp" "t.registers.val_input_X.in"
-= "t.registers._in_v_temp" "t.registers.val_input.out"
 "t.registers.clock_buffer[0].buf1.a"->"t.registers.clock_buffer[0].buf1._y"-
 ~("t.registers.clock_buffer[0].buf1.a")->"t.registers.clock_buffer[0].buf1._y"+
 "t.registers.clock_buffer[0].buf1._y"->"t.registers.clock_buffer[0].buf1.y"-
@@ -1032,14 +1050,9 @@
 = "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]"
 = "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].buf1.y"
 = "t.registers.clock_buffer[7].in" "t.registers.clock_buffer[7].buf1.a"
-= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]"
-= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].out[1]"
-= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].out[1]"
-= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].out[1]"
-= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].out[1]"
-= "t.registers.clock_buffer[2].out[0]" "t.registers.clock_buffer[2].out[1]"
-= "t.registers.clock_buffer[1].out[0]" "t.registers.clock_buffer[1].out[1]"
-= "t.registers.clock_buffer[0].out[0]" "t.registers.clock_buffer[0].out[1]"
+= "t.registers._in_v_temp" "t.registers.clk_dly.in"
+= "t.registers._in_v_temp" "t.registers.val_input_X.in"
+= "t.registers._in_v_temp" "t.registers.val_input.out"
 = "t.registers._clock" "t.registers.and_encoder[7].b"
 = "t.registers._clock" "t.registers.and_encoder[6].b"
 = "t.registers._clock" "t.registers.and_encoder[5].b"
diff --git a/test/unit_tests/register_write/test.prsim b/test/unit_tests/register_write/test.prsim
index 2895ba3..09d42e8 100644
--- a/test/unit_tests/register_write/test.prsim
+++ b/test/unit_tests/register_write/test.prsim
@@ -36,6 +36,8 @@ assert t.registers._out_encoder[3] 0
 set-qdi-channel-neutral "t.in" 5
 cycle
 assert t.registers._clock 0
+assert t.registers.ff[0].q 1
+assert t.registers.ff[1].q 1
 system "echo '[3] clock checked'"