From b59a57c3246b8880282dccfda997010de2633c4a Mon Sep 17 00:00:00 2001
From: alexmadison <git@mdsn.co.uk>
Date: Sat, 2 Apr 2022 17:37:56 +0200
Subject: [PATCH] changed write bit selectors from ands to Cels, to avoid
 selector hazards

---
 dataflow_neuro/registers.act | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index e3bf85c..58f5d5d 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -422,6 +422,7 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
 vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
     .supply = supply);
 
+
 // Address decoder
 decoder_dualrail<NcA, M> decoder(.supply = supply);
 (i:NcA:
@@ -437,10 +438,10 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
 
 // Write bit selector
 bool _w = in.d.d[NcA+NcW].t;
-AND2_X1 write_selectors[M];
+A_2C_B_X1 write_selectors[M];
 (i:M:
-    write_selectors[i].a = _w;
-    write_selectors[i].b = decoder.out[i];
+    write_selectors[i].c1 = _w;
+    write_selectors[i].c2 = decoder.out[i];
     write_selectors[i].vdd = supply.vdd;
     write_selectors[i].vss = supply.vss;
 )