diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act
index 8921da2..1dc3155 100644
--- a/dataflow_neuro/cell_lib_async.act
+++ b/dataflow_neuro/cell_lib_async.act
@@ -538,7 +538,7 @@ namespace tmpl {
         }
         }
 
-        def A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
+        defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
             bool _y;
             prs{
                 (~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
@@ -548,8 +548,6 @@ namespace tmpl {
             sizing {leak_adjust <- 1; 
                 p_n_mode <- 1;
                 y {-1}; _y{-1} }
-
-
         }
         }}
 
diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index b7808e3..557abf9 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -25,7 +25,7 @@
  *
  **************************************************************************
  */
-* 
+
 
 import "../../dataflow_neuro/cell_lib_async.act";
 import "../../dataflow_neuro/cell_lib_std.act";
@@ -51,7 +51,7 @@ namespace tmpl {
 //        - the last wl the word to write
 // data -> the data saved in the flip flop, sized wl x nw
 export template<pint log_nw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of<wl> data[2<<log_nw] ){
+defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power suppy; bool reset_B,reset_mem_B){
     bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
     //Validation of the input 
     vtree val_input(.in = in,.out = _in_v_temp, .supply = supply);
@@ -64,17 +64,18 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of<wl> data[2<<log_nw] ){
     delayprog<N_dly_cfg> dly(.in = _clock, .s = _in_a_temp, .supply = supply);
     sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
     //Reset Buffers
-    bool _reset_BX,_reset_BXX[_nw*w];
+    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*w];
     BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<_nw*wl> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss);
+    BUF_X1 reset_buf(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
+    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_BXX_mem,.vdd=supply.vdd,.vss=supply.vss);
     // Creating the different flip flop arrays
     bool _nw = 2<<log_nw;
     bool _word_idx = 0;
     bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
     andtree<log_nw> atree[_nw];
-    AND2_X1 and_encoder[_nw]
+    AND2_X1 and_encoder[_nw];
     sigbuf<wl> clock_buffer;
-    DFQ_R_X1 ff[_nw*wl];
+    DFFQ_R_X1 ff[_nw*wl];
     (k:_nw:atree_x[k].supply = supply;)
     (_word_idx:_nw:
         // Decoding the bit pattern to understand which word we are looking at
@@ -90,7 +91,7 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of<wl> data[2<<log_nw] ){
         // Activating the fake clock for the right word
         atree_x[_word_idx].out = _out_encoder[_word_idx];    
         and_encoder[_word_idx].a = _out_encoder[_word_idx];
-        and_encoder[_word_idx].b = _clock
+        and_encoder[_word_idx].b = _clock;
         and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
         and_encoder[_word_idx].vdd = supply.vdd;
         and_encoder[_word_idx].vss = supply.vss;
@@ -103,7 +104,7 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of<wl> data[2<<log_nw] ){
             ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx];
             ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw];
             ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
-            ff[_bit_idx*(1+_word_idx)].reset_B = reset_BXX[_bit_idx*(1+_word_idx)];
+            ff[_bit_idx*(1+_word_idx)].reset_B = reset_mem_BXX[_bit_idx*(1+_word_idx)];
             ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
             ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
         )