diff --git a/test/unit_tests/register_wrw/run/prsim.out b/test/unit_tests/register_wrw/run/prsim.out
index e3482d2..8ed22b6 100644
--- a/test/unit_tests/register_wrw/run/prsim.out
+++ b/test/unit_tests/register_wrw/run/prsim.out
@@ -369,6 +369,54 @@ WRONG ASSERT:	"t.out.d.d[3].f" has value X and not 0.
 WRONG ASSERT:	"t.out.d.d[3].t" has value X and not 0.
 [1] reset completed
 ----------------------------------------------------------
+	    408819 t.dly_cfg[0] : 1
+	    408819 t.dly_cfg[1] : 1
+	    408849 t.registers.ack_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    408878 t.registers.clk_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    410286 t.registers.clk_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    437146 t.registers.ack_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    468382 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.mu2[0]._s:=0]
+	    487766 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    488451 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    505166 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    505293 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    505462 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    505505 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    505517 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    506796 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    507029 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    507032 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    507070 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    507071 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    519823 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    519915 t.registers._clock_temp_inv : 1  [by t.registers._clock_temp:=0]
+	    522642 t.registers.clk_X.buf1._y : 0  [by t.registers._clock_temp_inv:=1]
+	    522644 t.registers._clock : 1  [by t.registers.clk_X.buf1._y:=0]
+	    522645 t.registers.ack_dly.and2[0]._y : 0  [by t.registers._clock:=1]
+	    524146 t.registers.ack_dly.dly[0].a : 1  [by t.registers.ack_dly.and2[0]._y:=0]
+	    524148 t.registers.ack_dly.dly[0]._y : 0  [by t.registers.ack_dly.dly[0].a:=1]
+	    524166 t.registers.ack_dly.dly[0].__y : 1  [by t.registers.ack_dly.dly[0]._y:=0]
+	    524285 t.registers.ack_dly.dly[0].___y : 0  [by t.registers.ack_dly.dly[0].__y:=1]
+	    530005 t.registers.ack_dly.dly[0].y : 1  [by t.registers.ack_dly.dly[0].___y:=0]
+	    530013 t.registers.ack_dly.mu2[0]._y : 0  [by t.registers.ack_dly.dly[0].y:=1]
+	    530067 t.registers.ack_dly._a[1] : 1  [by t.registers.ack_dly.mu2[0]._y:=0]
+	    580605 t.registers.ack_dly.and2[1]._y : 0  [by t.registers.ack_dly._a[1]:=1]
+	    580610 t.registers.ack_dly.dly[1].a : 1  [by t.registers.ack_dly.and2[1]._y:=0]
+	    581677 t.registers.ack_dly.dly[1]._y : 0  [by t.registers.ack_dly.dly[1].a:=1]
+	    581678 t.registers.ack_dly.dly[1].__y : 1  [by t.registers.ack_dly.dly[1]._y:=0]
+	    581816 t.registers.ack_dly.dly[1].___y : 0  [by t.registers.ack_dly.dly[1].__y:=1]
+	    581817 t.registers.ack_dly.dly[1].y : 1  [by t.registers.ack_dly.dly[1].___y:=0]
+	    581881 t.registers.ack_dly.dly[2]._y : 0  [by t.registers.ack_dly.dly[1].y:=1]
+	    582004 t.registers.ack_dly.dly[2].__y : 1  [by t.registers.ack_dly.dly[2]._y:=0]
+	    582006 t.registers.ack_dly.dly[2].___y : 0  [by t.registers.ack_dly.dly[2].__y:=1]
+	    582043 t.registers.ack_dly.dly[2].y : 1  [by t.registers.ack_dly.dly[2].___y:=0]
+	    582186 t.registers.ack_dly.mu2[1]._y : 0  [by t.registers.ack_dly.dly[2].y:=1]
+	    582237 t.registers._in_write.a : 1  [by t.registers.ack_dly.mu2[1]._y:=0]
+	    582679 t.registers.read_write_demux._out2_a_B : 0  [by t.registers._in_write.a:=1]
+	    582680 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 1  [by t.registers.read_write_demux._out2_a_B:=0]
+	    582689 t.registers.read_write_demux._out2_a_BX_t[0] : 0  [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=1]
+	    582690 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 1  [by t.registers.read_write_demux._out2_a_B:=0]
+	    582715 t.registers.read_write_demux._out2_a_BX_f[0] : 0  [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=1]
 [2] delay line set
 ----------------------------------------------------------
 	    383458 t.registers.ff[0].d : 1