diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act
index f3d6fd4..85f2523 100644
--- a/dataflow_neuro/chips.act
+++ b/dataflow_neuro/chips.act
@@ -80,7 +80,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
 
     power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){
 
     bool _reset_BX;
     BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
@@ -94,7 +94,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     // Register
     fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
     register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
-        .supply = supply, .reset_B = _reset_BX);
+        .supply = supply, .reset_B = reset_reg_B);
     fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
 
 
@@ -408,7 +408,7 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
     power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){
 
     // Reset buffers
     bool _reset_BX;
@@ -454,7 +454,7 @@ defproc texel_dualcore (bd<N_IN> in, out;
             .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
             .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
 
-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
             .supply = supply
             );
 
@@ -479,7 +479,7 @@ defproc texel_dualcore (bd<N_IN> in, out;
             .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
             .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
 
-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
             .supply = supply
             );