From ca0e5df048ce9afc51f76aa85df6fd4f5db9b10d Mon Sep 17 00:00:00 2001 From: Michele Date: Mon, 21 Feb 2022 13:01:45 +0100 Subject: [PATCH] prepared things for having unit test ready --- Makefile | 4 +- README.md | 2 +- dataflow_neuro/Makefile | 4 +- dataflow_neuro/__all__.act | 6 +- dataflow_neuro/cell_lib_async.act | 28 +++--- dataflow_neuro/cell_lib_async_test.act | 64 ++++++------- dataflow_neuro/primitives.act | 6 +- test/run.sh | 3 +- .../async_instantiate/run/prsim.out | 1 + .../unit_tests/async_instantiate/run/test.prs | 96 +++++++++++++++++++ test/unit_tests/async_instantiate/test.act | 60 ++++++++++++ test/unit_tests/async_instantiate/test.prsim | 0 test/unit_tests/fifo3_8bit/test.act | 2 +- test/unit_tests/fifo3_8bit/test.prsim | 1 - test/unit_tests/init.prs | 0 test/unit_tests/init_qdi.prsim | 3 - 16 files changed, 216 insertions(+), 64 deletions(-) create mode 100644 test/unit_tests/async_instantiate/run/prsim.out create mode 100644 test/unit_tests/async_instantiate/run/test.prs create mode 100644 test/unit_tests/async_instantiate/test.act create mode 100644 test/unit_tests/async_instantiate/test.prsim create mode 100644 test/unit_tests/init.prs diff --git a/Makefile b/Makefile index d1c8a44..7b6a657 100644 --- a/Makefile +++ b/Makefile @@ -20,8 +20,8 @@ # ----------------------------------------------------------------------------- TARGETACT=LICENSE -# template because its a template based appoach no syntesis so it would be wrong in syn -TARGETACTSUBDIR=template/dataflow_neuro +# tmpl because its a template based appoach no syntesis so it would be wrong in syn +TARGETACTSUBDIR=tmpl/dataflow_neuro SUBDIRS=dataflow_neuro diff --git a/README.md b/README.md index 2494da7..214d382 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # A dataflow template library for mixed signal neuromoric processors -the library will be installed in `$ACT_HOME/act/template/dataflow_neuro`. +the library will be installed in `$ACT_HOME/act/tmpl/dataflow_neuro`. This path is part of the default search path for any ACT tool. this library depends on stdlib (https://github.com/asyncvlsi/stdlib) diff --git a/dataflow_neuro/Makefile b/dataflow_neuro/Makefile index 583860d..edcef60 100644 --- a/dataflow_neuro/Makefile +++ b/dataflow_neuro/Makefile @@ -19,10 +19,10 @@ # # ----------------------------------------------------------------------------- -TARGETACT=__all__.act stdcells.act acells.act primitives.act +TARGETACT=__all__.act cell_lib_std.act cell_lib_async.act primitives.act SUBDIRS= # template because its a template based appoach no syntesis so it would be wrong in syn -TARGETACTSUBDIR=template/dataflow_neuro +TARGETACTSUBDIR=tmpl/dataflow_neuro include $(ACT_HOME)/scripts/Makefile.std diff --git a/dataflow_neuro/__all__.act b/dataflow_neuro/__all__.act index 60c97bd..ef1f594 100644 --- a/dataflow_neuro/__all__.act +++ b/dataflow_neuro/__all__.act @@ -22,6 +22,6 @@ ************************************************************************** */ -import template::dataflow_neuro::cell_lib_std; -import template::dataflow_neuro::cell_lib_async; -import template::dataflow_neuro::primitives; \ No newline at end of file +import tmpl::dataflow_neuro::cell_lib_std; +import tmpl::dataflow_neuro::cell_lib_async; +import tmpl::dataflow_neuro::primitives; \ No newline at end of file diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act index 3b2c8b4..51b5ac4 100644 --- a/dataflow_neuro/cell_lib_async.act +++ b/dataflow_neuro/cell_lib_async.act @@ -24,9 +24,9 @@ ************************************************************************** */ -namespace async_template { - - export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) { +namespace tmpl { + namespace dataflow_neuro{ + export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) { bool _y; prs{ (~p1 & ~c1)|~pr_B -> _y+ @@ -41,7 +41,7 @@ namespace async_template { } } - export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) { + export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) { prs{ (~p1 & ~c1)|~pr_B -> y- c1 & n1 & n2 & sr_B -> y+ @@ -54,7 +54,7 @@ namespace async_template { } - export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1, vdd, vss) + export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1; bool vdd, vss) { prs{ ~p1 & ~c1 -> y+ @@ -65,7 +65,7 @@ namespace async_template { y {-1}} } - export defcell A_1C1P_B (bool! y; bool? c1, p1, vdd, vss) + export defcell A_1C1P_B (bool! y; bool? c1, p1; bool vdd, vss) { bool _y; prs{ @@ -79,7 +79,7 @@ namespace async_template { } - export defcell A_1C1P (bool! y; bool? c1, p1, vdd, vss) + export defcell A_1C1P (bool! y; bool? c1, p1; bool vdd, vss) { prs{ ~p1 & ~c1 -> y+ @@ -90,7 +90,7 @@ namespace async_template { y {-1}} } - export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1, vdd, vss) + export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss) { prs{ ~p1 & ~p2 & ~c1 -> y+ @@ -101,7 +101,7 @@ namespace async_template { y {-1}} } - export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2, vdd, vss) + export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2; bool vdd, vss) { bool _y; prs{ @@ -115,7 +115,7 @@ namespace async_template { } - export defcell A_1C2P (bool! y; bool? c1, p1, p2, vdd, vss) + export defcell A_1C2P (bool! y; bool? c1, p1, p2; bool vdd, vss) { prs{ ~p1 & ~p2 & ~c1 -> y+ @@ -126,7 +126,7 @@ namespace async_template { y {-1}} } - export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5, n1, n2, pr_B, sr_B, vdd, vss) + export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5, n1, n2, pr_B, sr_B; bool vdd, vss) { prs{ (~p1 & ~p2 & ~p3 & ~c1)|(~p4&~p5&~c1)|~pr_B -> y+ @@ -137,7 +137,7 @@ namespace async_template { y {-1}} } - export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss) + export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss) { bool _y; prs{ @@ -151,7 +151,7 @@ namespace async_template { y {-1}; _y{-1}} } - export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss) + export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss) { bool _y; prs{ @@ -439,7 +439,7 @@ namespace async_template { p_n_mode <- 1; y {-1}} } - } + }} diff --git a/dataflow_neuro/cell_lib_async_test.act b/dataflow_neuro/cell_lib_async_test.act index 0e306af..7139015 100644 --- a/dataflow_neuro/cell_lib_async_test.act +++ b/dataflow_neuro/cell_lib_async_test.act @@ -26,35 +26,35 @@ */ import "cell_lib_async.act"; - -async_template::A_1C1P2N_RB_X1 cell1; -async_template::A_1C1P2N_R_X1 cell2; -async_template::A_1C1P_1N_X1 cell3; -async_template::A_1C1P_B cell4; -async_template::A_1C1P cell5; -async_template::A_1C2P1N_X1 cell6; -async_template::A_1C2P_B_X1 cell7; -async_template::A_1C2P cell8; -async_template::A_1C3P2P2N_R_X1 cell9; -async_template::A_2C2N2N_RB_X1 cell10; -async_template::A_2C2N2N_RB_X2 cell11; -async_template::A_2C2N2N_RB_X4 cell12; -async_template::A_2C2N2N_R_X1 cell13; -async_template::A_2C2N_R_B_X2 cell14; -async_template::A_2C2N_R_B_X4 cell15; -async_template::A_2C2N_R_X1 cell16; -async_template::A_2C_B_X1 cell17; -async_template::A_2C_RB_X1 cell18; -async_template::A_2C_R_X1 cell19; -async_template::A_2C_X1 cell20; -async_template::A_3C_RB_X1 cell21; -async_template::A_3C_RB_X2 cell22; -async_template::A_3C_RB_X4 cell23; -async_template::A_3C_R_X1 cell24; -async_template::A_3C_X1 cell25; -async_template::A_4C_RB_X1 cell26; -async_template::A_4C_RB_X2 cell27; -async_template::A_4C_RB_X4 cell28; -async_template::A_4C_R_X1 cell29; -async_template::A_4P1N1N_B_X1 cell30; -async_template::A_4P1N1N_X1 cell31; \ No newline at end of file +open tmpl::dataflow_neuro; +A_1C1P2N_RB_X1 cell1; +A_1C1P2N_R_X1 cell2; +A_1C1P_1N_X1 cell3; +A_1C1P_B cell4; +A_1C1P cell5; +A_1C2P1N_X1 cell6; +A_1C2P_B_X1 cell7; +A_1C2P cell8; +A_1C3P2P2N_R_X1 cell9; +A_2C2N2N_RB_X1 cell10; +A_2C2N2N_RB_X2 cell11; +A_2C2N2N_RB_X4 cell12; +A_2C2N2N_R_X1 cell13; +A_2C2N_R_B_X2 cell14; +A_2C2N_R_B_X4 cell15; +A_2C2N_R_X1 cell16; +A_2C_B_X1 cell17; +A_2C_RB_X1 cell18; +A_2C_R_X1 cell19; +A_2C_X1 cell20; +A_3C_RB_X1 cell21; +A_3C_RB_X2 cell22; +A_3C_RB_X4 cell23; +A_3C_R_X1 cell24; +A_3C_X1 cell25; +A_4C_RB_X1 cell26; +A_4C_RB_X2 cell27; +A_4C_RB_X4 cell28; +A_4C_R_X1 cell29; +A_4P1N1N_B_X1 cell30; +A_4P1N1N_X1 cell31; \ No newline at end of file diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 45a2e29..45f2833 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -21,12 +21,12 @@ * ************************************************************************** */ -import template::dataflow_neuro::cell_lib_std; -import template::dataflow_neuro::cell_lib_async; +import tmpl::dataflow_neuro::cell_lib_std; +import tmpl::dataflow_neuro::cell_lib_async; import std::channel; open std::channel; -namespace template { +namespace tmpl { namespace dataflow_neuro { // @ole talk to rajit, we use valid the wrong way arround according to stdlib diff --git a/test/run.sh b/test/run.sh index e3f4d57..1d922f1 100755 --- a/test/run.sh +++ b/test/run.sh @@ -37,8 +37,7 @@ run_test () { fi } -if [ ! ( command -v aflat && command -v prsim ) ]; -then +if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then echo "${bold}Error:${bold} aflat & prsim necessary for tests." exit 1 fi diff --git a/test/unit_tests/async_instantiate/run/prsim.out b/test/unit_tests/async_instantiate/run/prsim.out new file mode 100644 index 0000000..d9a9c2d --- /dev/null +++ b/test/unit_tests/async_instantiate/run/prsim.out @@ -0,0 +1 @@ +cell27._y cell25.c3 cell18._y cell14._y cell27.pr_B cell21.y cell23.c3 cell10._y cell30.p3 cell20.c1 cell10.n1 cell30._y cell12.sr_B cell8.c1 cell16.c2 cell2.p1 cell28.c2 cell5.c1 cell21._y cell19.c2 cell6.p2 cell9.pr_B cell9.p3 cell4.p1 cell28.sr_B cell11.pr_B cell26.c4 cell9.n2 cell27.c2 cell12.c2 cell28.pr_B cell21.pr_B cell22.pr_B cell11.c2 cell13.y cell9.n1 cell1.n1 cell12.c1 cell28.c4 cell1.n2 cell22.sr_B cell26.y cell11.n2 cell13.n4 cell15.rs_B cell6.c1 cell28._y cell2.n2 cell10.pr_B cell16.y cell16.c1 cell11.sr_B cell15._y cell2.pr_B cell11._y cell20.y cell21.c2 cell22.c1 cell27.sr_B cell4.y cell10.n4 cell23.pr_B cell2.sr_B cell6.p1 cell9.p4 cell23._y cell11.c1 cell9.sr_B cell9.c1 cell27.y cell29.c3 cell12.n1 cell1.sr_B cell29.sr_B cell13.n3 cell13.n2 cell11.n4 cell15.n2 cell15.rp_B cell2.y cell3.n1 cell15.c2 cell26.c3 cell24.c2 cell17._y cell28.c1 cell6.n1 cell14.n1 cell31.n1 cell21.c3 cell27.c3 cell19.sr_B cell26._y cell7._y cell20.c2 cell10.n2 cell9.p2 cell14.rs_B cell31.y cell13.pr_B cell31.p1 cell30.n2 cell18.sr_B cell10.y cell6.y cell24.sr_B cell14.n2 cell30.n1 cell22.y cell10.sr_B cell10.n3 cell13.c2 cell13.n1 cell24.y cell12.pr_B cell29.pr_B cell24.c1 cell16.n1 cell24.pr_B cell28.c3 cell17.c2 cell11.n3 cell16.rs_B cell4._y cell14.c1 cell8.p2 cell14.c2 cell8.p1 cell15.n1 cell15.y cell23.c2 cell18.c1 cell7.p2 cell9.y cell7.y cell29.c1 cell30.p1 cell12.n3 cell11.n1 cell26.pr_B cell29.y cell22._y cell13.c1 cell18.y cell7.c1 cell19.y cell27.c4 cell25.c1 cell21.c1 cell30.y cell1.y cell26.c1 cell17.c1 cell2.n1 cell25.y cell5.y cell30.p4 cell31.p3 cell25.c2 cell3.p1 cell9.p5 cell9.p1 cell26.sr_B cell19.c1 cell8.y cell23.c1 cell18.c2 cell7.p1 cell22.c2 cell23.y cell14.rp_B cell30.p2 cell29.c4 cell23.sr_B cell1.c1 cell26.c2 cell3.y cell10.c1 cell16.n2 cell21.sr_B cell24.c3 cell31.p4 cell1.pr_B cell12.n2 cell31.p2 cell11.y cell12.n4 cell12._y cell18.pr_B cell10.c2 cell2.c1 cell5.p1 cell31.n2 cell13.sr_B cell12.y cell27.c1 cell1._y cell14.y cell16.rp_B cell15.c1 cell4.c1 cell29.c2 cell17.y cell19.pr_B cell3.c1 cell22.c3 cell28.y cell1.p1 diff --git a/test/unit_tests/async_instantiate/run/test.prs b/test/unit_tests/async_instantiate/run/test.prs new file mode 100644 index 0000000..61fe11d --- /dev/null +++ b/test/unit_tests/async_instantiate/run/test.prs @@ -0,0 +1,96 @@ +~"cell26.c1"&~"cell26.c2"&~"cell26.c3"&~"cell26.c4"|~"cell26.pr_B"->"cell26._y"+ +"cell26.c1"&"cell26.c2"&"cell26.c3"&"cell26.c4"&"cell26.sr_B"->"cell26._y"- +"cell26._y"->"cell26.y"- +~("cell26._y")->"cell26.y"+ +~"cell16.c1"&~"cell16.c2"|~"cell16.rp_B"->"cell16.y"+ +"cell16.c1"&"cell16.c2"&"cell16.n1"&"cell16.n2"&"cell16.rs_B"->"cell16.y"- +~"cell8.p1"&~"cell8.p2"&~"cell8.c1"->"cell8.y"+ +"cell8.c1"->"cell8.y"- +~"cell22.c1"&~"cell22.c2"&~"cell22.c3"|~"cell22.pr_B"->"cell22._y"+ +"cell22.c1"&"cell22.c2"&"cell22.c3"&"cell22.sr_B"->"cell22._y"- +"cell22._y"->"cell22.y"- +~("cell22._y")->"cell22.y"+ +~"cell19.c1"&~"cell19.c2"|~"cell19.pr_B"->"cell19.y"+ +"cell19.c1"&"cell19.c2"&"cell19.sr_B"->"cell19.y"- +~"cell12.c1"&~"cell12.c2"|~"cell12.pr_B"->"cell12._y"+ +"cell12.c1"&"cell12.c2"&("cell12.n1"&"cell12.n2"|"cell12.n3"&"cell12.n4")&"cell12.sr_B"->"cell12._y"- +"cell12._y"->"cell12.y"- +~("cell12._y")->"cell12.y"+ +~"cell30.p1"&~"cell30.p2"&~"cell30.p3"&~"cell30.p4"->"cell30._y"+ +"cell30.n1"|"cell30.n2"->"cell30._y"- +"cell30._y"->"cell30.y"- +~("cell30._y")->"cell30.y"+ +~"cell17.c1"&~"cell17.c2"->"cell17._y"+ +"cell17.c1"&"cell17.c2"->"cell17._y"- +"cell17._y"->"cell17.y"- +~("cell17._y")->"cell17.y"+ +~"cell14.c1"&~"cell14.c2"|~"cell14.rp_B"->"cell14._y"+ +"cell14.c1"&"cell14.c2"&"cell14.n1"&"cell14.n2"&"cell14.rs_B"->"cell14._y"- +"cell14._y"->"cell14.y"- +~("cell14._y")->"cell14.y"+ +~"cell7.p1"&~"cell7.p2"&~"cell7.c1"->"cell7._y"- +"cell7.c1"->"cell7._y"+ +"cell7._y"->"cell7.y"- +~("cell7._y")->"cell7.y"+ +~"cell1.p1"&~"cell1.c1"|~"cell1.pr_B"->"cell1._y"+ +"cell1.c1"&"cell1.n1"&"cell1.n2"&"cell1.sr_B"->"cell1._y"- +"cell1._y"->"cell1.y"- +~("cell1._y")->"cell1.y"+ +~"cell21.c1"&~"cell21.c2"&~"cell21.c3"|~"cell21.pr_B"->"cell21._y"+ +"cell21.c1"&"cell21.c2"&"cell21.c3"&"cell21.sr_B"->"cell21._y"- +"cell21._y"->"cell21.y"- +~("cell21._y")->"cell21.y"+ +~"cell18.c1"&~"cell18.c2"|~"cell18.pr_B"->"cell18._y"+ +"cell18.c1"&"cell18.c2"&"cell18.sr_B"->"cell18._y"- +"cell18._y"->"cell18.y"- +~("cell18._y")->"cell18.y"+ +~"cell15.c1"&~"cell15.c2"|~"cell15.rp_B"->"cell15._y"+ +"cell15.c1"&"cell15.c2"&"cell15.n1"&"cell15.n2"&"cell15.rs_B"->"cell15._y"- +"cell15._y"->"cell15.y"- +~("cell15._y")->"cell15.y"+ +~"cell13.c1"&~"cell13.c2"|~"cell13.pr_B"->"cell13.y"+ +"cell13.c1"&"cell13.c2"&("cell13.n1"&"cell13.n2"|"cell13.n3"&"cell13.n4")&"cell13.sr_B"->"cell13.y"- +~"cell11.c1"&~"cell11.c2"|~"cell11.pr_B"->"cell11._y"+ +"cell11.c1"&"cell11.c2"&("cell11.n1"&"cell11.n2"|"cell11.n3"&"cell11.n4")&"cell11.sr_B"->"cell11._y"- +"cell11._y"->"cell11.y"- +~("cell11._y")->"cell11.y"+ +~"cell28.c1"&~"cell28.c2"&~"cell28.c3"&~"cell28.c4"|~"cell28.pr_B"->"cell28._y"+ +"cell28.c1"&"cell28.c2"&"cell28.c3"&"cell28.c4"&"cell28.sr_B"->"cell28._y"- +"cell28._y"->"cell28.y"- +~("cell28._y")->"cell28.y"+ +~"cell24.c1"&~"cell24.c2"&~"cell24.c3"|~"cell24.pr_B"->"cell24.y"+ +"cell24.c1"&"cell24.c2"&"cell24.c3"&"cell24.sr_B"->"cell24.y"- +~"cell23.c1"&~"cell23.c2"&~"cell23.c3"|~"cell23.pr_B"->"cell23._y"+ +"cell23.c1"&"cell23.c2"&"cell23.c3"&"cell23.sr_B"->"cell23._y"- +"cell23._y"->"cell23.y"- +~("cell23._y")->"cell23.y"+ +~"cell10.c1"&~"cell10.c2"|~"cell10.pr_B"->"cell10._y"+ +"cell10.c1"&"cell10.c2"&("cell10.n1"&"cell10.n2"|"cell10.n3"&"cell10.n4")&"cell10.sr_B"->"cell10._y"- +"cell10._y"->"cell10.y"- +~("cell10._y")->"cell10.y"+ +~"cell3.p1"&~"cell3.c1"->"cell3.y"+ +"cell3.c1"&"cell3.n1"->"cell3.y"- +~"cell29.c1"&~"cell29.c2"&~"cell29.c3"&~"cell29.c4"|~"cell29.pr_B"->"cell29.y"+ +"cell29.c1"&"cell29.c2"&"cell29.c3"&"cell29.c4"&"cell29.sr_B"->"cell29.y"- +~"cell25.c1"&~"cell25.c2"&~"cell25.c3"->"cell25.y"+ +"cell25.c1"&"cell25.c2"&"cell25.c3"->"cell25.y"- +~"cell5.p1"&~"cell5.c1"->"cell5.y"+ +"cell5.c1"->"cell5.y"- +~"cell4.p1"&~"cell4.c1"->"cell4._y"- +"cell4.c1"->"cell4._y"+ +"cell4._y"->"cell4.y"- +~("cell4._y")->"cell4.y"+ +~"cell31.p1"&~"cell31.p2"&~"cell31.p3"&~"cell31.p4"->"cell31.y"+ +"cell31.n1"|"cell31.n2"->"cell31.y"- +~"cell27.c1"&~"cell27.c2"&~"cell27.c3"&~"cell27.c4"|~"cell27.pr_B"->"cell27._y"+ +"cell27.c1"&"cell27.c2"&"cell27.c3"&"cell27.c4"&"cell27.sr_B"->"cell27._y"- +"cell27._y"->"cell27.y"- +~("cell27._y")->"cell27.y"+ +~"cell20.c1"&~"cell20.c2"->"cell20.y"+ +"cell20.c1"&"cell20.c2"->"cell20.y"- +~"cell9.p1"&~"cell9.p2"&~"cell9.p3"&~"cell9.c1"|~"cell9.p4"&~"cell9.p5"&~"cell9.c1"|~"cell9.pr_B"->"cell9.y"+ +"cell9.c1"&"cell9.n1"&"cell9.n2"&"cell9.sr_B"->"cell9.y"- +~"cell6.p1"&~"cell6.p2"&~"cell6.c1"->"cell6.y"+ +"cell6.c1"&"cell6.n1"->"cell6.y"- +~"cell2.p1"&~"cell2.c1"|~"cell2.pr_B"->"cell2.y"- +"cell2.c1"&"cell2.n1"&"cell2.n2"&"cell2.sr_B"->"cell2.y"+ diff --git a/test/unit_tests/async_instantiate/test.act b/test/unit_tests/async_instantiate/test.act new file mode 100644 index 0000000..39a5643 --- /dev/null +++ b/test/unit_tests/async_instantiate/test.act @@ -0,0 +1,60 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_async.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/cell_lib_async.act"; +open tmpl::dataflow_neuro; +A_1C1P2N_RB_X1 cell1; +A_1C1P2N_R_X1 cell2; +A_1C1P_1N_X1 cell3; +A_1C1P_B cell4; +A_1C1P cell5; +A_1C2P1N_X1 cell6; +A_1C2P_B_X1 cell7; +A_1C2P cell8; +A_1C3P2P2N_R_X1 cell9; +A_2C2N2N_RB_X1 cell10; +A_2C2N2N_RB_X2 cell11; +A_2C2N2N_RB_X4 cell12; +A_2C2N2N_R_X1 cell13; +A_2C2N_R_B_X2 cell14; +A_2C2N_R_B_X4 cell15; +A_2C2N_R_X1 cell16; +A_2C_B_X1 cell17; +A_2C_RB_X1 cell18; +A_2C_R_X1 cell19; +A_2C_X1 cell20; +A_3C_RB_X1 cell21; +A_3C_RB_X2 cell22; +A_3C_RB_X4 cell23; +A_3C_R_X1 cell24; +A_3C_X1 cell25; +A_4C_RB_X1 cell26; +A_4C_RB_X2 cell27; +A_4C_RB_X4 cell28; +A_4C_R_X1 cell29; +A_4P1N1N_B_X1 cell30; +A_4P1N1N_X1 cell31; \ No newline at end of file diff --git a/test/unit_tests/async_instantiate/test.prsim b/test/unit_tests/async_instantiate/test.prsim new file mode 100644 index 0000000..e69de29 diff --git a/test/unit_tests/fifo3_8bit/test.act b/test/unit_tests/fifo3_8bit/test.act index 3bd4ead..b1f3968 100644 --- a/test/unit_tests/fifo3_8bit/test.act +++ b/test/unit_tests/fifo3_8bit/test.act @@ -1,4 +1,4 @@ -import template::dataflow_neuro +import tmpl::dataflow_neuro defproc fifo3_8bit (avMx1of2<8> A; avMx1of2<8> Y) { diff --git a/test/unit_tests/fifo3_8bit/test.prsim b/test/unit_tests/fifo3_8bit/test.prsim index 8e80632..9fe02f0 100644 --- a/test/unit_tests/fifo3_8bit/test.prsim +++ b/test/unit_tests/fifo3_8bit/test.prsim @@ -5,7 +5,6 @@ set t.Y.a 0 cycle system "echo 'reset completed'" status X -set Reset 0 mode run cycle diff --git a/test/unit_tests/init.prs b/test/unit_tests/init.prs new file mode 100644 index 0000000..e69de29 diff --git a/test/unit_tests/init_qdi.prsim b/test/unit_tests/init_qdi.prsim index 6fb4c18..b9af213 100644 --- a/test/unit_tests/init_qdi.prsim +++ b/test/unit_tests/init_qdi.prsim @@ -1,11 +1,8 @@ initialize load-scm "helper.scm" random -set GND 0 -set Vdd 1 mode reset -set Reset 1 cycle status U