diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act
index 0ea0419..6fca411 100644
--- a/dataflow_neuro/registers.act
+++ b/dataflow_neuro/registers.act
@@ -146,7 +146,7 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
         (i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
         vtree<lognw+wl> val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
         // Acknowledgment
-        //delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
+        delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
         // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
         delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
         INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);