From cd445d173688efd6c8ce794aa4d9173339ba19fa Mon Sep 17 00:00:00 2001 From: alexmadison Date: Mon, 2 May 2022 15:26:03 +0200 Subject: [PATCH] added inverters on every 4th synapse targetting line --- dataflow_neuro/chips.act | 12 +++++-- test/unit_tests/texel_dualcore/test.prsim | 38 +++++++++++------------ 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act index c200942..0065ba8 100644 --- a/dataflow_neuro/chips.act +++ b/dataflow_neuro/chips.act @@ -194,11 +194,13 @@ defproc texel_core (avMx1of2 in, out; // Device debug hard-wired safety (reg0, b05 = DEV_DEBUG) // Stops the possibility of dev_mon being high while some other sig is high. // Otherwise boom. + // Also the 4th monitor line to each synapse is active LOW, needs inverter. bool DEV_DEBUG; pint NSMX4 = N_SYN_MON_X/4; // Self explanatory sigbuf sb_DEV_DEBUG(.in = register.data[0].d[5].t, .supply = supply); DEV_DEBUG = sb_DEV_DEBUG.out[0]; + INV_X1 syn_targ_set_high_inv[NSMX4]; [NSMX4 >= 1 -> AND2_X1 ands_devmon[NSMX4]; (i:NSMX4: @@ -207,10 +209,16 @@ defproc texel_core (avMx1of2 in, out; ands_devmon[i].y = syn_mon_x_buf.in[1+i*4]; ands_devmon[i].vdd = supply.vdd; ands_devmon[i].vss = supply.vss; + + syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4]; + syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4]; + syn_targ_set_high_inv[i].vdd = supply.vdd; + syn_targ_set_high_inv[i].vss = supply.vss; + ) - // Wire up the non-ANDed lines. + // Wire up the remaining lines. (i:N_SYN_MON_X: - [~(i%4 = 1) -> + [(~(i%4 = 1)) & (~(i%4=3))-> syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i]; ] ) diff --git a/test/unit_tests/texel_dualcore/test.prsim b/test/unit_tests/texel_dualcore/test.prsim index 70820e1..e55ffe5 100644 --- a/test/unit_tests/texel_dualcore/test.prsim +++ b/test/unit_tests/texel_dualcore/test.prsim @@ -14903,63 +14903,63 @@ assert c.c1_nrn_mon_y[5] 0 assert c.c1_syn_mon_x[0] 0 assert c.c1_syn_mon_x[1] 0 assert c.c1_syn_mon_x[2] 0 -assert c.c1_syn_mon_x[3] 0 +assert c.c1_syn_mon_x[3] 1 assert c.c1_syn_mon_x[4] 0 assert c.c1_syn_mon_x[5] 0 assert c.c1_syn_mon_x[6] 0 -assert c.c1_syn_mon_x[7] 0 +assert c.c1_syn_mon_x[7] 1 assert c.c1_syn_mon_x[8] 0 assert c.c1_syn_mon_x[9] 0 assert c.c1_syn_mon_x[10] 0 -assert c.c1_syn_mon_x[11] 0 +assert c.c1_syn_mon_x[11] 1 assert c.c1_syn_mon_x[12] 0 assert c.c1_syn_mon_x[13] 0 assert c.c1_syn_mon_x[14] 0 -assert c.c1_syn_mon_x[15] 0 +assert c.c1_syn_mon_x[15] 1 assert c.c1_syn_mon_x[16] 0 assert c.c1_syn_mon_x[17] 0 assert c.c1_syn_mon_x[18] 0 -assert c.c1_syn_mon_x[19] 0 +assert c.c1_syn_mon_x[19] 1 assert c.c1_syn_mon_x[20] 0 assert c.c1_syn_mon_x[21] 0 assert c.c1_syn_mon_x[22] 0 -assert c.c1_syn_mon_x[23] 0 +assert c.c1_syn_mon_x[23] 1 assert c.c1_syn_mon_x[24] 0 assert c.c1_syn_mon_x[25] 0 assert c.c1_syn_mon_x[26] 0 -assert c.c1_syn_mon_x[27] 0 +assert c.c1_syn_mon_x[27] 1 assert c.c1_syn_mon_x[28] 0 assert c.c1_syn_mon_x[29] 0 assert c.c1_syn_mon_x[30] 0 -assert c.c1_syn_mon_x[31] 0 +assert c.c1_syn_mon_x[31] 1 assert c.c1_syn_mon_x[32] 0 assert c.c1_syn_mon_x[33] 0 assert c.c1_syn_mon_x[34] 0 -assert c.c1_syn_mon_x[35] 0 +assert c.c1_syn_mon_x[35] 1 assert c.c1_syn_mon_x[36] 0 assert c.c1_syn_mon_x[37] 0 assert c.c1_syn_mon_x[38] 0 -assert c.c1_syn_mon_x[39] 0 +assert c.c1_syn_mon_x[39] 1 assert c.c1_syn_mon_x[40] 0 assert c.c1_syn_mon_x[41] 0 assert c.c1_syn_mon_x[42] 0 -assert c.c1_syn_mon_x[43] 0 +assert c.c1_syn_mon_x[43] 1 assert c.c1_syn_mon_x[44] 0 assert c.c1_syn_mon_x[45] 0 assert c.c1_syn_mon_x[46] 0 -assert c.c1_syn_mon_x[47] 0 +assert c.c1_syn_mon_x[47] 1 assert c.c1_syn_mon_x[48] 0 assert c.c1_syn_mon_x[49] 0 assert c.c1_syn_mon_x[50] 0 -assert c.c1_syn_mon_x[51] 0 +assert c.c1_syn_mon_x[51] 1 assert c.c1_syn_mon_x[52] 0 assert c.c1_syn_mon_x[53] 0 assert c.c1_syn_mon_x[54] 0 -assert c.c1_syn_mon_x[55] 0 +assert c.c1_syn_mon_x[55] 1 assert c.c1_syn_mon_x[56] 0 assert c.c1_syn_mon_x[57] 0 assert c.c1_syn_mon_x[58] 0 -assert c.c1_syn_mon_x[59] 0 +assert c.c1_syn_mon_x[59] 1 # disable targetting @@ -15025,11 +15025,11 @@ assert c.in.a 0 assert c.c1_syn_mon_x[0] 0 assert c.c1_syn_mon_x[1] 0 assert c.c1_syn_mon_x[2] 0 -assert c.c1_syn_mon_x[3] 0 +assert c.c1_syn_mon_x[3] 1 assert c.c1_syn_mon_x[4] 0 assert c.c1_syn_mon_x[5] 0 assert c.c1_syn_mon_x[6] 0 -assert c.c1_syn_mon_x[7] 0 +assert c.c1_syn_mon_x[7] 1 assert c.c1_syn_mon_x[8] 0 assert c.c1_syn_mon_x[9] 0 assert c.c1_syn_mon_x[10] 0 @@ -15060,11 +15060,11 @@ assert c.in.a 1 assert c.c1_syn_mon_x[0] 0 assert c.c1_syn_mon_x[1] 0 assert c.c1_syn_mon_x[2] 0 -assert c.c1_syn_mon_x[3] 0 +assert c.c1_syn_mon_x[3] 1 assert c.c1_syn_mon_x[4] 0 assert c.c1_syn_mon_x[5] 1 assert c.c1_syn_mon_x[6] 0 -assert c.c1_syn_mon_x[7] 0 +assert c.c1_syn_mon_x[7] 1 assert c.c1_syn_mon_x[8] 0 assert c.c1_syn_mon_x[9] 0 assert c.c1_syn_mon_x[10] 0