From df1aae7690667c7113a2a77f138342a3671a9745 Mon Sep 17 00:00:00 2001
From: alexmadison <git@mdsn.co.uk>
Date: Fri, 1 Apr 2022 16:57:44 +0200
Subject: [PATCH] added S cells for register

---
 dataflow_neuro/cell_lib_async.act | 67 +++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act
index 274927a..755c371 100644
--- a/dataflow_neuro/cell_lib_async.act
+++ b/dataflow_neuro/cell_lib_async.act
@@ -130,6 +130,60 @@ namespace tmpl {
             y {-1}}
         }
 
+        // export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 | ~pr_B-> _y+
+        //     c1&n1&sr_B -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+        // export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
+        // {
+        // bool _y;
+        // prs{
+        //     ~c1 & ~sr-> _y+
+        //     c1&n1 | pr -> _y-
+        //     _y => y-
+        //     }
+        // sizing {leak_adjust <- 1; 
+        //         p_n_mode <- 1;
+        //     y {-4}; _y{-1}}
+        // }
+
+
+        export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 | ~pr_B-> _y+
+            c1&n1&n2&sr_B -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+        export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
+        {
+        bool _y;
+        prs{
+            ~c1 & ~sr-> _y+
+            c1&n1&n2 | pr -> _y-
+            _y => y-
+            }
+        sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-4}; _y{-1}}
+        }
+
+
         export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
         {
         prs{
@@ -354,6 +408,19 @@ namespace tmpl {
                 p_n_mode <- 1;
             y {-1}; _y{-1}}
         }
+
+        export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
+        {
+        prs{
+            (~c1 & ~c2) | ~pr_B -> y+
+            c1 & c2 & n1 & sr_B -> y-
+        }
+        sizing {    
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+            y {-1}}
+        }
+
         export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
         {
             bool _y;