From df97903436bcb4df41a7c736be871f3b51a0dcb8 Mon Sep 17 00:00:00 2001 From: Michele Date: Mon, 21 Feb 2022 16:44:08 +0100 Subject: [PATCH] test celement tree is working --- dataflow_neuro/cell_lib_async.act | 14 ++++++ dataflow_neuro/cell_lib_std.act | 22 ++++++++- dataflow_neuro/primitives.act | 6 ++- dataflow_neuro/treegates.act | 46 +++++++++++-------- .../primitive_instantiate/run/prsim.out | 1 + .../primitive_instantiate/run/test.prs | 8 ++++ .../unit_tests/primitive_instantiate/test.act | 34 ++++++++++++++ .../primitive_instantiate/test.prsim | 0 8 files changed, 109 insertions(+), 22 deletions(-) create mode 100644 test/unit_tests/primitive_instantiate/run/prsim.out create mode 100644 test/unit_tests/primitive_instantiate/run/test.prs create mode 100644 test/unit_tests/primitive_instantiate/test.act create mode 100644 test/unit_tests/primitive_instantiate/test.prsim diff --git a/dataflow_neuro/cell_lib_async.act b/dataflow_neuro/cell_lib_async.act index 51b5ac4..9e97175 100644 --- a/dataflow_neuro/cell_lib_async.act +++ b/dataflow_neuro/cell_lib_async.act @@ -300,6 +300,20 @@ namespace tmpl { y {-1}} } + export defcell A_3C_B_X1 (bool ! y; bool? c1, c2, c3; bool? vdd, vss) + { + bool _y; + prs{ + ~c1 & ~c2 & ~c3 -> _y+ + c1 & c2 & c3 -> _y- + _y => y- + } + sizing { + leak_adjust <- 1; + p_n_mode <- 1; + y {-1}; _y{-1}} + } + export defcell A_3C_RB_X1 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss) { bool _y; diff --git a/dataflow_neuro/cell_lib_std.act b/dataflow_neuro/cell_lib_std.act index 6a8254c..15dedd8 100644 --- a/dataflow_neuro/cell_lib_std.act +++ b/dataflow_neuro/cell_lib_std.act @@ -70,16 +70,34 @@ namespace tmpl { _y => y- } } - + export defcell BUF_X1<: buf() + { + sizing { _y {-1}; y {-1} } + } export defcell BUF_X2<: buf() { sizing { _y {-1}; y {-2} } } - + export defcell BUF_X3<: buf() + { + sizing { _y {-1.5}; y {-3} } + } export defcell BUF_X4<: buf() { sizing { _y {-1.5}; y {-4,2} } } + export defcell BUF_X6<: buf() + { + sizing { _y {-3}; y {-6,2} } + } + export defcell BUF_X8<: buf() + { + sizing { _y {-4,2}; y {-8,4} } + } + export defcell BUF_X12<: buf() + { + sizing { _y {-6,2}; y {-12,4} } + } /*-- simple gates --*/ diff --git a/dataflow_neuro/primitives.act b/dataflow_neuro/primitives.act index 45f2833..e4c33e1 100644 --- a/dataflow_neuro/primitives.act +++ b/dataflow_neuro/primitives.act @@ -21,8 +21,10 @@ * ************************************************************************** */ -import tmpl::dataflow_neuro::cell_lib_std; -import tmpl::dataflow_neuro::cell_lib_async; +import "cell_lib_async.act"; +import "cell_lib_std.act"; +// import tmpl::dataflow_neuro; +// import tmpl::dataflow_neuro; import std::channel; open std::channel; diff --git a/dataflow_neuro/treegates.act b/dataflow_neuro/treegates.act index d68557c..c839c69 100644 --- a/dataflow_neuro/treegates.act +++ b/dataflow_neuro/treegates.act @@ -20,14 +20,20 @@ * these sources, You must maintain the Source Location visible in its * documentation. * - ************************************************************************** -namespace std { + **************************************************************************/ +import "../../dataflow_neuro/cell_lib_async.act"; +import "../../dataflow_neuro/cell_lib_std.act"; -export namespace gates { +namespace tmpl { + namespace dataflow_neuro { /* * Build an OR-gate tree (NOR/NAND/optional INV) */ + + + +export deftype power (bool?! vdd, vss) { } export template defproc ortree (bool? in[N]; bool out) { @@ -175,17 +181,25 @@ defproc ctree (bool? in[N]; bool out) bool tmp[end+j..end+j]; [ i+1 >= end -> /*-- last piece: use either a 2 input C-element --*/ - C2Els[tree2Index](.c1 = tmp[i], .c2 = tmp[i+1], .y = tmp[end+j]) + C2Els[tree2Index].c1 = tmp[i]; + C2Els[tree2Index].c2 = tmp[i+1]; + C2Els[tree2Index].y = tmp[end+j]; tree2Index = tree2Index +1; i = end; [] i+2 >= end -> /*-- last piece: use either a 3 input C-element --*/ - C3Els[tree3Index](.c1 = tmp[i], .c2 = tmp[i+1], .c3 = tmp[i+2], .y = tmp[end+j]) + C3Els[tree3Index].c1 = tmp[i]; + C3Els[tree3Index].c2 = tmp[i+1]; + C3Els[tree3Index].c3 = tmp[i+2]; + C3Els[tree3Index].y = tmp[end+j]; + tree3Index = tree3Index +1; i = end; [] else -> /*-- more to come; so use a two input C-element --*/ - C2Els[tree2Index](.c1 = tmp[i], .c2 = tmp[i+1], .y = tmp[end+j]) + C2Els[tree2Index].c1 = tmp[i]; + C2Els[tree2Index].c2 = tmp[i+1]; + C2Els[tree2Index].y = tmp[end+j]; tree2Index = tree2Index +1; i = i + 2; ] @@ -206,24 +220,20 @@ defproc sigbuf (bool? in; bool! out; power supply) /* -- just use a sized driver here -- */ [ N <= 4 -> - BUF_X1 buf; - + BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 5 & N <= 7 -> - BUF_X2 buf; + BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 8 & N <= 10 -> - BUF_X3 buf; + BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 11 & N <= 14 -> - BUF_X4 buf; + BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 15 & N <= 18 -> - BUF_X6 buf; + BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 19 & N <= 29 -> - BUF_X8 buf; + BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); [] N >= 30 & N <= 42 -> - BUF_X12 buf; + BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss); ] - buf.a = in; - buf.y = out; - buf.vdd = supply.vdd; - buf.vss = supply.vss; } +}} diff --git a/test/unit_tests/primitive_instantiate/run/prsim.out b/test/unit_tests/primitive_instantiate/run/prsim.out new file mode 100644 index 0000000..f5bec95 --- /dev/null +++ b/test/unit_tests/primitive_instantiate/run/prsim.out @@ -0,0 +1 @@ +buff_test.out buff_test.buf1._y buff_test.in diff --git a/test/unit_tests/primitive_instantiate/run/test.prs b/test/unit_tests/primitive_instantiate/run/test.prs new file mode 100644 index 0000000..070fe1b --- /dev/null +++ b/test/unit_tests/primitive_instantiate/run/test.prs @@ -0,0 +1,8 @@ +"buff_test.buf1.a"->"buff_test.buf1._y"- +~("buff_test.buf1.a")->"buff_test.buf1._y"+ +"buff_test.buf1._y"->"buff_test.buf1.y"- +~("buff_test.buf1._y")->"buff_test.buf1.y"+ += "buff_test.supply.vdd" "buff_test.buf1.vdd" += "buff_test.supply.vss" "buff_test.buf1.vss" += "buff_test.out" "buff_test.buf1.y" += "buff_test.in" "buff_test.buf1.a" diff --git a/test/unit_tests/primitive_instantiate/test.act b/test/unit_tests/primitive_instantiate/test.act new file mode 100644 index 0000000..865677d --- /dev/null +++ b/test/unit_tests/primitive_instantiate/test.act @@ -0,0 +1,34 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library. + * It's the testing facility for cell_lib_std.act + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + +import "../../dataflow_neuro/treegates.act"; + +open tmpl::dataflow_neuro; + +sigbuf<3> buff_test; + diff --git a/test/unit_tests/primitive_instantiate/test.prsim b/test/unit_tests/primitive_instantiate/test.prsim new file mode 100644 index 0000000..e69de29