From e49866323c55174a8f7f827a5e04219a46e6d070 Mon Sep 17 00:00:00 2001 From: Michele Date: Mon, 7 Mar 2022 16:36:01 +0100 Subject: [PATCH] register_write works --- dataflow_neuro/cell_lib_std.act | 16 +- dataflow_neuro/registers.act | 86 +-- test/unit_tests/flipflop/run/prsim.out | 76 ++- test/unit_tests/flipflop/test.prsim | 5 +- test/unit_tests/register_write/run/prsim.out | 589 ++++++++--------- test/unit_tests/register_write/run/test.prs | 652 ++++++------------- test/unit_tests/register_write/test.act | 2 +- test/unit_tests/register_write/test.prsim | 9 +- 8 files changed, 598 insertions(+), 837 deletions(-) diff --git a/dataflow_neuro/cell_lib_std.act b/dataflow_neuro/cell_lib_std.act index 878b624..5be7803 100644 --- a/dataflow_neuro/cell_lib_std.act +++ b/dataflow_neuro/cell_lib_std.act @@ -373,22 +373,22 @@ namespace tmpl { } sizing { _en{-2}; y{-2,2} } } - export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss) + export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q; bool? vdd,vss) { - bool _clk, __clk, _mqi,_mqib,_sqi,_sqib; + bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib; prs { // Creating delayed versions of the clock - clk => _clk- - _clk => __clk- + clk_B => _clk_B- + _clk_B => __clk_B- - (~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+ - (d & __clk)|(reset_B & _mqi & _clk) -> _mqib- + (~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+ + ((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib- _mqib => _mqi- - (~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+ - (_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib- + (~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+ + ((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib- _sqib => _sqi- _sqib => q- diff --git a/dataflow_neuro/registers.act b/dataflow_neuro/registers.act index 554fda4..d9f7129 100644 --- a/dataflow_neuro/registers.act +++ b/dataflow_neuro/registers.act @@ -41,72 +41,72 @@ namespace tmpl { namespace dataflow_neuro { // Circuit for storing, reading and writing registers using AER // The block has the parameters: -// log_nw -> log2(number of words), parameters you can store +// lognw -> log2(number of words), parameters you can store // wl -> word length, length of each word // N_dly_cfg -> the number of config bits in the ACK delay line // The block has the pins: // in -> input data, // - the first bit is write/read_B -// - the next log_nw bits describe the location, +// - the next lognw bits describe the location, // - the last wl the word to write // data -> the data saved in the flip flop, sized wl x nw -export template -defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of data[2< +defproc register_rw (avMx1of2<1+lognw+wl> in; d1of data[1< _in_temp; - (i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];) - vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply); + Mx1of2<1+lognw+wl> _in_temp; + (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];) + vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply); sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply); // Generation of the fake clock pulse delayprog clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply); - sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply); + INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss); + sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply); // Sending back to the ackowledge delayprog ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply); sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply); //Reset Buffers - bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl]; + bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl]; BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss); - sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply); + sigbuf reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply); // Creating the different flip flop arrays - bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl]; - andtree atree[_nw]; - AND2_X1 and_encoder[_nw]; - sigbuf clock_buffer[_nw]; - DFFQ_R_X1 ff[_nw*wl]; - pint _bitval; - (k:_nw:atree[k].supply = supply;) - (_word_idx:_nw: + bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl]; + andtree atree[nw]; + AND2_X1 and_encoder[nw]; + sigbuf clock_buffer[nw]; + DFFQ_R_X1 ff[nw*wl]; + pint bitval; + (k:nw:atree[k].supply = supply;) + (word_idx:nw: // Decoding the bit pattern to understand which word we are looking at - (pin_idx:log_nw: - _bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j - [_bitval = 1 -> - atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t; - [] _bitval = 0 -> - atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f; - []_bitval >= 2 -> {false : "fuck"}; + (pin_idx:lognw: + bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j + [bitval = 1 -> + atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t; + [] bitval = 0 -> + atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f; + []bitval >= 2 -> {false : "fuck"}; ] ) // Activating the fake clock for the right word - atree[_word_idx].out = _out_encoder[_word_idx]; - and_encoder[_word_idx].a = _out_encoder[_word_idx]; - and_encoder[_word_idx].b = _clock; - and_encoder[_word_idx].y = _clock_word_temp[_word_idx]; - and_encoder[_word_idx].vdd = supply.vdd; - and_encoder[_word_idx].vss = supply.vss; - clock_buffer[_word_idx].in = _clock_word_temp[_word_idx]; - clock_buffer[_word_idx].supply = supply; + atree[word_idx].out = _out_encoder[word_idx]; + and_encoder[word_idx].a = _out_encoder[word_idx]; + and_encoder[word_idx].b = _clock; + and_encoder[word_idx].y = _clock_word_temp[word_idx]; + and_encoder[word_idx].vdd = supply.vdd; + and_encoder[word_idx].vss = supply.vss; + clock_buffer[word_idx].in = _clock_word_temp[word_idx]; + clock_buffer[word_idx].supply = supply; // Describing all the FF and their connection - (_bit_idx:wl: - clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)]; - // ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)]; - // ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t; - // ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx]; - // ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)]; - // ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd; - // ff[_bit_idx*(1+_word_idx)].vss = supply.vss; + (bit_idx:wl: + ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx]; + ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t; + ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx]; + ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)]; + ff[bit_idx+word_idx*(wl)].vdd = supply.vdd; + ff[bit_idx+word_idx*(wl)].vss = supply.vss; ) ) } diff --git a/test/unit_tests/flipflop/run/prsim.out b/test/unit_tests/flipflop/run/prsim.out index 2d87273..b83d500 100644 --- a/test/unit_tests/flipflop/run/prsim.out +++ b/test/unit_tests/flipflop/run/prsim.out @@ -1,35 +1,57 @@ t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk [0] start test - 1 t.d : 0 + 1 Reset : 0 1 t.clk : 0 - 7093 t.ff._mqib : 1 [by t.d:=0] - 7095 t.ff._mqi : 0 [by t.ff._mqib:=1] + 1 t.d : 0 + 3 t.ff._mqib : 1 [by t.d:=0] + 4756 t.ff._mqi : 0 [by t.ff._mqib:=1] + 5893 t.ff._sqib : 1 [by t.ff._mqi:=0] + 6007 t.ff._sqi : 0 [by t.ff._sqib:=1] + 7093 t._reset_B : 1 [by Reset:=0] 10468 t.ff._clk : 1 [by t.clk:=0] - 11605 t.ff.__clk : 0 [by t.ff._clk:=1] - 11848 t.ff._sqib : 1 [by t.ff._mqi:=0] - 11962 t.ff._sqi : 0 [by t.ff._sqib:=1] - 77214 t.q : 0 [by t.ff._sqib:=1] + 12194 t.ff.__clk : 0 [by t.ff._clk:=1] + 71259 t.q : 0 [by t.ff._sqib:=1] - 77214 Reset : 0 - 78940 t._reset_B : 1 [by Reset:=0] [1] reset completed - 78940 t.clk : 1 - 78979 t.ff._clk : 0 [by t.clk:=1] - 78994 t.ff.__clk : 1 [by t.ff._clk:=0] + 71259 t.clk : 1 + 71298 t.ff._clk : 0 [by t.clk:=1] + 71313 t.ff.__clk : 1 [by t.ff._clk:=0] [2] tested d = 0, clk rise - 78994 t.clk : 0 - 79485 t.ff._clk : 1 [by t.clk:=0] - 79498 t.ff.__clk : 0 [by t.ff._clk:=1] - 79498 t.d : 1 - 79498 t.clk : 1 - 79538 t.ff._clk : 0 [by t.clk:=1] - 79953 t.ff.__clk : 1 [by t.ff._clk:=0] - 79973 t.ff._mqib : 0 [by t.ff.__clk:=1] - 86034 t.ff._mqi : 1 [by t.ff._mqib:=0] - 86034 t.clk : 0 - 86081 t.ff._clk : 1 [by t.clk:=0] - 86097 t.ff.__clk : 0 [by t.ff._clk:=1] - 130179 t.ff._sqib : 0 [by t.ff._clk:=1] - 130183 t.q : 1 [by t.ff._sqib:=0] - 143903 t.ff._sqi : 1 [by t.ff._sqib:=0] + 71313 t.clk : 0 + 71804 t.ff._clk : 1 [by t.clk:=0] + 71817 t.ff.__clk : 0 [by t.ff._clk:=1] + 71817 t.d : 1 + 71817 t.clk : 1 + 71857 t.ff._clk : 0 [by t.clk:=1] + 72272 t.ff.__clk : 1 [by t.ff._clk:=0] + 72292 t.ff._mqib : 0 [by t.ff.__clk:=1] + 78353 t.ff._mqi : 1 [by t.ff._mqib:=0] + 78353 t.d : 0 + 78353 t.clk : 0 +WARNING: unstable `t.ff._mqib'+ +>> cause: t.ff._clk (val: 1) + 78369 t.ff._clk : 1 [by t.clk:=0] +WARNING: weak-interference `t.ff._mqi' +>> cause: t.ff._mqib (val: X) +>> time: 78400 + 78400 t.ff._mqib : X [by t.ff._clk:=1] + 78404 t.ff._mqib : 0 [by t.ff._clk:=1] +WARNING: weak-unstable `t.ff._sqib'- +>> cause: t.ff._mqi (val: X) +>> time: 87529 + 87529 t.ff._mqi : X [by t.ff._mqib:=0] + 87544 t.ff._mqi : 1 [by t.ff._mqib:=0] +WARNING: weak-interference `t.ff._sqi' +>> cause: t.ff._sqib (val: X) +>> time: 92093 +WARNING: weak-interference `t.q' +>> cause: t.ff._sqib (val: X) +>> time: 92093 + 92093 t.ff._sqib : X [by t.ff._mqi:=1] + 92148 t.q : X [by t.ff._sqib:=X] + 122467 t.ff.__clk : 0 [by t.ff._clk:=1] + 129024 t.ff._sqi : X [by t.ff._sqib:=X] + 135341 t.ff._sqib : 0 [by t.ff._mqi:=1] + 165121 t.q : 1 [by t.ff._sqib:=0] + 186994 t.ff._sqi : 1 [by t.ff._sqib:=0] [3] tested d = 1, clk rise and fall diff --git a/test/unit_tests/flipflop/test.prsim b/test/unit_tests/flipflop/test.prsim index 8f6475b..0b7f1a0 100644 --- a/test/unit_tests/flipflop/test.prsim +++ b/test/unit_tests/flipflop/test.prsim @@ -1,13 +1,13 @@ watchall system "echo '[0] start test'" -set Reset 1 +set Reset 0 set t.d 0 set t.clk 0 cycle status X mode run assert t.q 0 -set Reset 0 + cycle assert t.q 0 system "echo '[1] reset completed'" @@ -21,6 +21,7 @@ set t.d 1 cycle set t.clk 1 cycle +set t.d 0 assert t.q 0 set t.clk 0 cycle diff --git a/test/unit_tests/register_write/run/prsim.out b/test/unit_tests/register_write/run/prsim.out index 05b2824..59ef79d 100644 --- a/test/unit_tests/register_write/run/prsim.out +++ b/test/unit_tests/register_write/run/prsim.out @@ -1,298 +1,299 @@ -t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.clk_dly.and2[0]._y t.in.d.d[0].t t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers._clock_buffer_out[0] t.registers.val_input.ct.in[1] t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.registers.atree[2].in[1] t.dly_cfg[0] t.registers.ff[4].__clk t.registers._in_v_temp t.registers.atree[1].in[0] t.registers._out_encoder[2] t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.val_input.ct.in[0] t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.in.v t.registers._clock_word_temp[5] t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.in.d.d[4].t t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers._clock_word_temp[3] t.registers._out_encoder[7] t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers._out_encoder[4] t.registers.val_input.ct.in[3] t.registers.ff[7]._mqi t.registers._out_encoder[5] t.registers.ff[5].q t.in.d.d[1].t t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers._clock_word_temp[4] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ack_dly.dly[2].___y t.registers._clock_word_temp[7] t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers._clock_word_temp[6] t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.atree[0].in[1] t.registers.clk_dly._a[1] t.registers.val_input.ct.in[4] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.val_input.OR2_tf[3]._y t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.clk_dly.dly[0].___y t.registers.ff[8].q t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers._out_encoder[6] t.registers.ff[6].reset_B t.registers.clock_buffer[4].buf1._y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.clk_dly.dly[0]._y t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.ff[14].q t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.atree[6].and2s[0]._y t.registers.atree[0].and2s[0]._y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.clock_buffer[2].buf1._y t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.clk_dly.dly[0].y t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.atree[7].and2s[0]._y t.registers.ff[4]._clk t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ff[12]._mqi t.registers.atree[4].and2s[0]._y t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.and_encoder[0]._y t.registers.ff[13]._mqi t.registers.and_encoder[6]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ff[8].reset_B t.registers.and_encoder[5]._y t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.atree[3].and2s[0]._y t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.atree[2].and2s[0]._y t.registers.ff[11]._sqib t.registers.clock_buffer[7].buf1._y t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.clock_buffer[5].buf1._y t.registers.val_input_X.buf1._y t.registers.ff[11].q t.registers.and_encoder[7]._y t.registers.val_input.OR2_tf[0]._y t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.clock_buffer[6].buf1._y t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.atree[5].and2s[0]._y t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.and_encoder[1]._y t.registers.and_encoder[4]._y t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.val_input.OR2_tf[4]._y t.registers.ff[11].d t.registers.val_input.ct.C2Els[0]._y t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.val_input.ct.C3Els[0]._y t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B +t.registers.ff[4].clk_B t.registers._clock_word_temp[0] t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.registers.ff[0].clk_B t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.ack_dly.dly[1].__y t.registers.ff[0].d t.registers.clk_dly.and2[0]._y t.registers.val_input.ct.in[1] t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ff[5].__clk_B t.registers.ack_dly.dly[1].___y t.registers.ff[4]._clk_B t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[6].clk_B t.registers.atree[2].in[1] t.dly_cfg[0] t.registers._in_v_temp t.registers._out_encoder[2] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers.val_input.ct.in[0] t.registers._in_a_temp t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.in.v t.registers.ff[3]._clk_B t.registers.clk_dly.dly[2].y t.in.d.d[4].t t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.ack_dly.dly[0].___y t.registers.val_input.ct.in[3] t.registers.ff[1].d t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.atree[1].in[0] t.registers.ack_dly.dly[2].___y t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.clk_dly._a[1] t.registers.atree[0].in[1] t.registers.ff[2].__clk_B t.registers.val_input.ct.in[4] t.registers.val_input.OR2_tf[3]._y t.registers.clk_X.buf1._y t.registers.ff[7].__clk_B t.registers.clk_dly.dly[0].___y t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[7]._clk_B t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[1]._clk_B t.registers.clk_dly.dly[0]._y t.registers.val_input.ct.in[2] t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ack_dly.dly[2].y t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.clk_dly.mu2[0]._s t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ack_dly.dly[0].a t.registers.ff[0]._clk_B t.registers.clock_buffer[2].buf1._y t.registers.clk_dly.dly[1].__y t.registers.ff[2].clk_B t.registers.ff[6]._clk_B t.registers.clk_dly.dly[0].y t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ack_dly.dly[1]._y t.registers.and_encoder[0]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ack_dly.dly[1].y t.registers.ack_dly.and2[1]._y t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[3].__clk_B t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.ff[6].__clk_B t.registers.ack_dly.dly[1].a t.registers.ff[4].__clk_B t.registers.atree[2].and2s[0]._y t.registers.ff[1].__clk_B t.registers.val_input_X.buf1._y t.registers.ack_dly.dly[2].__y t.registers.val_input.OR2_tf[0]._y t.registers.ff[0].__clk_B t.registers.ff[5]._clk_B t.registers.and_encoder[1]._y t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.clk_dly.dly[2].___y t.registers.val_input.OR2_tf[4]._y t.registers.ack_input_X.buf1._y t.registers.val_input.ct.C2Els[0]._y t.registers.ack_dly.mu2[1]._y t.registers.val_input.ct.C3Els[0]._y t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[2]._clk_B t.registers.ack_dly.mu2[0]._s [0] start test - 16472 t.in.d.d[0].f : 0 - 16472 t.data[1].d[1] : 0 - 16472 t.data[1].d[0] : 0 - 16472 t.data[0].d[1] : 0 - 16472 t.data[0].d[0] : 0 - 16472 t.in.d.d[4].t : 0 - 16472 t.in.d.d[4].f : 0 - 16472 t.registers.atree[2].in[1] : 0 - 16472 t.in.d.d[1].f : 0 - 16472 t.registers.atree[0].in[1] : 0 - 16472 t.registers.atree[1].in[0] : 0 - 16472 t.in.d.d[0].t : 0 - 16472 t.registers.atree[0].in[0] : 0 - 16472 t.in.d.d[1].t : 0 - 16485 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0] - 16487 t.registers.atree[6].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] - 16488 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] - 16491 t.registers._out_encoder[6] : 0 [by t.registers.atree[6].and2s[0]._y:=1] - 16492 t.registers.atree[4].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 16506 t.registers.and_encoder[6]._y : 1 [by t.registers._out_encoder[6]:=0] - 16511 t.registers.atree[3].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] - 16512 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 16519 t.registers.val_input.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0] - 16566 t.registers._out_encoder[3] : 0 [by t.registers.atree[3].and2s[0]._y:=1] - 16887 t.registers.atree[1].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 16963 t.registers.atree[7].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] - 18198 t.registers.atree[2].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] - 18620 t.registers._out_encoder[2] : 0 [by t.registers.atree[2].and2s[0]._y:=1] - 22533 t.registers.atree[5].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] - 22534 t.registers._out_encoder[5] : 0 [by t.registers.atree[5].and2s[0]._y:=1] - 22535 t.registers.and_encoder[5]._y : 1 [by t.registers._out_encoder[5]:=0] - 25617 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1] - 30209 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1] - 30415 t.registers.and_encoder[3]._y : 1 [by t.registers._out_encoder[3]:=0] - 30697 t.registers._clock_word_temp[3] : 0 [by t.registers.and_encoder[3]._y:=1] - 31306 t.registers._out_encoder[7] : 0 [by t.registers.atree[7].and2s[0]._y:=1] - 31309 t.registers.and_encoder[7]._y : 1 [by t.registers._out_encoder[7]:=0] - 31465 t.registers.clock_buffer[3].buf1._y : 1 [by t.registers._clock_word_temp[3]:=0] - 41699 t.registers._out_encoder[1] : 0 [by t.registers.atree[1].and2s[0]._y:=1] - 42250 t.registers.and_encoder[1]._y : 1 [by t.registers._out_encoder[1]:=0] - 42740 t.registers._clock_word_temp[5] : 0 [by t.registers.and_encoder[5]._y:=1] - 43321 t.registers._clock_word_temp[1] : 0 [by t.registers.and_encoder[1]._y:=1] - 43694 t.registers.clock_buffer[5].buf1._y : 1 [by t.registers._clock_word_temp[5]:=0] - 44402 t.registers.clock_buffer[1].buf1._y : 1 [by t.registers._clock_word_temp[1]:=0] - 46299 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1] - 53437 t.registers._clock_word_temp[6] : 0 [by t.registers.and_encoder[6]._y:=1] - 53750 t.registers._clock_word_temp[7] : 0 [by t.registers.and_encoder[7]._y:=1] - 54732 t.registers.clock_buffer[7].buf1._y : 1 [by t.registers._clock_word_temp[7]:=0] - 59740 t.registers._out_encoder[4] : 0 [by t.registers.atree[4].and2s[0]._y:=1] - 59758 t.registers.and_encoder[4]._y : 1 [by t.registers._out_encoder[4]:=0] - 60570 t.registers.val_input.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0] - 63771 t.registers._clock_word_temp[4] : 0 [by t.registers.and_encoder[4]._y:=1] - 64573 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1] - 67334 t.registers.and_encoder[2]._y : 1 [by t.registers._out_encoder[2]:=0] - 68165 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] - 68667 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0] - 68870 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] - 70724 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] - 72094 t.registers._clock_word_temp[2] : 0 [by t.registers.and_encoder[2]._y:=1] - 72233 t.registers.clock_buffer[2].buf1._y : 1 [by t.registers._clock_word_temp[2]:=0] - 81838 t.registers.val_input.OR2_tf[4]._y : 1 [by t.in.d.d[4].f:=0] - 86157 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[1]:=0] - 86226 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1] - 107907 t.registers.clock_buffer[6].buf1._y : 1 [by t.registers._clock_word_temp[6]:=0] - 108672 t.registers.clock_buffer[4].buf1._y : 1 [by t.registers._clock_word_temp[4]:=0] - 108683 t.registers._clock_buffer_out[0] : 0 [by t.registers.clock_buffer[4].buf1._y:=1] - 118184 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1] - 169970 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[4]:=0] - 170174 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1] - 170189 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[6]:=0] - 170190 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1] - 170227 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp:=0] - 170339 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1] - 170929 t.registers.val_input_X.buf1._y : 1 [by t.registers._in_v_temp:=0] - 170969 t.in.v : 0 [by t.registers.val_input_X.buf1._y:=1] - 217851 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0] - 218108 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1] - 218195 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0] - 218489 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1] -t.registers.ff[4].q t.registers.ff[15].reset_B t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.dly_cfg[0] t.registers.ff[4].__clk t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers.clk_dly.and2[1]._y t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers.ff[7]._mqi t.registers.ff[5].q t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers.ack_dly.dly[2].___y t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers.ack_dly.mu2[0]._y t.registers.clk_dly._a[1] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.ff[8].q t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers.ff[6].reset_B t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.ff[14].q t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.ff[4]._clk t.registers.ff[12]._mqi t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.ff[13]._mqi t.registers.ff[8].reset_B t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.ff[11]._sqib t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.ff[11].q t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.ff[11].d t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B - 218489 Reset : 0 - 218490 t._reset_B : 1 [by Reset:=0] - 220296 t.registers.reset_buf_BX._y : 0 [by t._reset_B:=1] - 220497 t.registers.reset_buf_BXX._y : 0 [by t._reset_B:=1] - 221087 t.registers._reset_mem_BX : 1 [by t.registers.reset_buf_BXX._y:=0] - 221265 t.registers.reset_bufarray.buf6._y : 0 [by t.registers._reset_mem_BX:=1] - 221505 t.registers._reset_BX : 1 [by t.registers.reset_buf_BX._y:=0] - 222068 t.registers._reset_mem_BXX[0] : 1 [by t.registers.reset_bufarray.buf6._y:=0] + 115040 t.in.d.d[0].f : 0 + 115040 Reset : 0 + 115040 t.in.d.d[4].t : 0 + 115040 t.in.d.d[1].f : 0 + 115040 t.in.d.d[4].f : 0 + 115040 t.registers.atree[2].in[1] : 0 + 115040 t.registers.atree[0].in[1] : 0 + 115040 t.registers.atree[1].in[0] : 0 + 115040 t.registers.ff[0].d : 0 + 115040 t.registers.atree[0].in[0] : 0 + 115040 t.registers.ff[1].d : 0 + 115058 t._reset_B : 1 [by Reset:=0] + 115127 t.registers.reset_buf_BXX._y : 0 [by t._reset_B:=1] + 115138 t.registers._reset_mem_BX : 1 [by t.registers.reset_buf_BXX._y:=0] + 115179 t.registers.val_input.OR2_tf[1]._y : 1 [by t.registers.ff[1].d:=0] + 115243 t.registers.val_input.OR2_tf[0]._y : 1 [by t.registers.ff[0].d:=0] + 115258 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1] + 115383 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1] + 115384 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[1]:=0] + 115421 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1] + 115542 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0] + 116281 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1] + 116894 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] + 117006 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1] + 119043 t.registers.atree[2].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] + 119053 t.registers.val_input.OR2_tf[4]._y : 1 [by t.in.d.d[4].f:=0] + 119093 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1] + 119350 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[4]:=0] + 119437 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1] + 119731 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[6]:=0] + 119732 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1] + 119800 t.registers.atree[1].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] + 121009 t.registers._out_encoder[1] : 0 [by t.registers.atree[1].and2s[0]._y:=1] + 121538 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp:=0] + 121599 t.registers.and_encoder[1]._y : 1 [by t.registers._out_encoder[1]:=0] + 121716 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1] + 121739 t.registers.val_input_X.buf1._y : 1 [by t.registers._in_v_temp:=0] + 121880 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0] + 121902 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1] + 122402 t.registers._clock_word_temp[1] : 0 [by t.registers.and_encoder[1]._y:=1] + 122749 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0] + 122882 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1] + 123934 t.in.v : 0 [by t.registers.val_input_X.buf1._y:=1] + 136624 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0] + 151404 t.registers.reset_buf_BX._y : 0 [by t._reset_B:=1] + 151763 t.registers._reset_BX : 1 [by t.registers.reset_buf_BX._y:=0] + 152286 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] + 152530 t.registers.clock_buffer[1].buf1._y : 1 [by t.registers._clock_word_temp[1]:=0] + 152751 t.registers.ff[2].clk_B : 0 [by t.registers.clock_buffer[1].buf1._y:=1] + 152758 t.registers.ff[2]._clk_B : 1 [by t.registers.ff[2].clk_B:=0] + 152781 t.registers.ff[3]._clk_B : 1 [by t.registers.ff[2].clk_B:=0] + 159471 t.registers.ff[2].__clk_B : 0 [by t.registers.ff[2]._clk_B:=1] + 159941 t.registers.atree[3].and2s[0]._y : 1 [by t.registers.atree[2].in[1]:=0] + 160032 t.registers._out_encoder[3] : 0 [by t.registers.atree[3].and2s[0]._y:=1] + 162221 t.registers.and_encoder[3]._y : 1 [by t.registers._out_encoder[3]:=0] + 162228 t.registers._clock_word_temp[3] : 0 [by t.registers.and_encoder[3]._y:=1] + 165015 t.registers.clock_buffer[3].buf1._y : 1 [by t.registers._clock_word_temp[3]:=0] + 165121 t.registers.ff[6].clk_B : 0 [by t.registers.clock_buffer[3].buf1._y:=1] + 165199 t.registers.ff[6]._clk_B : 1 [by t.registers.ff[6].clk_B:=0] + 165396 t.registers.ff[7]._clk_B : 1 [by t.registers.ff[6].clk_B:=0] + 165851 t.registers.ff[7].__clk_B : 0 [by t.registers.ff[7]._clk_B:=1] + 166402 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0] + 166414 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] + 166555 t.registers._out_encoder[2] : 0 [by t.registers.atree[2].and2s[0]._y:=1] + 166567 t.registers.and_encoder[2]._y : 1 [by t.registers._out_encoder[2]:=0] + 166818 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] + 166924 t.registers.reset_bufarray.buf3._y : 0 [by t.registers._reset_mem_BX:=1] + 169823 t.registers._reset_mem_BXX[0] : 1 [by t.registers.reset_bufarray.buf3._y:=0] + 171094 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1] + 171096 t.registers.ff[1]._clk_B : 1 [by t.registers.ff[0].clk_B:=0] + 172483 t.registers._clock_word_temp[2] : 0 [by t.registers.and_encoder[2]._y:=1] + 173732 t.registers.clock_buffer[2].buf1._y : 1 [by t.registers._clock_word_temp[2]:=0] + 175389 t.registers.ff[0]._clk_B : 1 [by t.registers.ff[0].clk_B:=0] + 175555 t.registers.ff[0].__clk_B : 0 [by t.registers.ff[0]._clk_B:=1] + 175631 t.registers.ff[1].__clk_B : 0 [by t.registers.ff[1]._clk_B:=1] + 177231 t.registers.ff[4].clk_B : 0 [by t.registers.clock_buffer[2].buf1._y:=1] + 177306 t.registers.ff[4]._clk_B : 1 [by t.registers.ff[4].clk_B:=0] + 177444 t.registers.ff[4].__clk_B : 0 [by t.registers.ff[4]._clk_B:=1] + 177576 t.registers.ff[5]._clk_B : 1 [by t.registers.ff[4].clk_B:=0] + 182839 t.registers.ff[5].__clk_B : 0 [by t.registers.ff[5]._clk_B:=1] + 184195 t.registers.ff[6].__clk_B : 0 [by t.registers.ff[6]._clk_B:=1] + 210242 t.registers.ff[3].__clk_B : 0 [by t.registers.ff[3]._clk_B:=1] +t.registers._clock_temp t.registers.ack_dly._a[1] t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.ack_dly.dly[1].__y t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.dly_cfg[0] t.registers.clk_dly.and2[1]._y t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.clk_dly.dly[1].y t.registers.clk_dly.dly[2].y t.registers.clk_dly.dly[1].a t.registers.ack_dly.dly[0].___y t.registers.ack_dly.dly[2].___y t.registers.ack_dly.mu2[0]._y t.registers.clk_dly._a[1] t.registers.clk_X.buf1._y t.registers.clk_dly.dly[1].___y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.clk_dly.dly[1]._y t.registers.ack_dly.dly[2].y t.registers.clk_dly.mu2[1]._y t.registers.clk_dly.mu2[0]._s t.registers.ack_dly.dly[0]._y t.registers.ack_dly.dly[0].a t.registers.clk_dly.dly[1].__y t.registers.clk_dly.mu2[0]._y t.registers.ack_dly.dly[1]._y t.registers.ack_dly.dly[1].y t.registers.ack_dly.and2[1]._y t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ack_dly.dly[1].a t.registers.ack_dly.dly[2].__y t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.clk_dly.dly[2].___y t.registers.ack_input_X.buf1._y t.registers.ack_dly.mu2[1]._y t.registers.ack_dly.dly[0].__y t.registers.ack_dly.mu2[0]._s [1] reset completed - 222068 t.dly_cfg[0] : 1 - 222068 t.dly_cfg[1] : 1 - 222090 t.registers.ack_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1] - 222232 t.registers.ack_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1] - 222915 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1] - 224263 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1] - 254391 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0] - 254524 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1] - 270186 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0] - 270545 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1] - 284661 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0] - 284882 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1] - 284889 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0] - 284919 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1] - 291632 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0] - 349093 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1] - 349184 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0] - 351373 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1] - 351380 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0] - 354167 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1] - 354273 t.registers.clk_X.buf1._y : 1 [by t.registers._clock_temp:=0] - 354351 t.registers._clock : 0 [by t.registers.clk_X.buf1._y:=1] - 354626 t.registers.ack_dly.and2[0]._y : 1 [by t.registers._clock:=0] - 373622 t.registers.ack_dly.dly[0].a : 0 [by t.registers.ack_dly.and2[0]._y:=1] - 374077 t.registers.ack_dly.dly[0]._y : 1 [by t.registers.ack_dly.dly[0].a:=0] - 374089 t.registers.ack_dly.dly[0].__y : 0 [by t.registers.ack_dly.dly[0]._y:=1] - 374493 t.registers.ack_dly.dly[0].___y : 1 [by t.registers.ack_dly.dly[0].__y:=0] - 374505 t.registers.ack_dly.dly[0].y : 0 [by t.registers.ack_dly.dly[0].___y:=1] - 380421 t.registers.ack_dly.mu2[0]._y : 1 [by t.registers.ack_dly.dly[0].y:=0] - 384697 t.registers.ack_dly._a[1] : 0 [by t.registers.ack_dly.mu2[0]._y:=1] - 387596 t.registers.ack_dly.and2[1]._y : 1 [by t.registers.ack_dly._a[1]:=0] - 391891 t.registers.ack_dly.dly[1].a : 0 [by t.registers.ack_dly.and2[1]._y:=1] - 391893 t.registers.ack_dly.dly[1]._y : 1 [by t.registers.ack_dly.dly[1].a:=0] - 396428 t.registers.ack_dly.dly[1].__y : 0 [by t.registers.ack_dly.dly[1]._y:=1] - 397677 t.registers.ack_dly.dly[1].___y : 1 [by t.registers.ack_dly.dly[1].__y:=0] - 401176 t.registers.ack_dly.dly[1].y : 0 [by t.registers.ack_dly.dly[1].___y:=1] - 401342 t.registers.ack_dly.dly[2]._y : 1 [by t.registers.ack_dly.dly[1].y:=0] - 401417 t.registers.ack_dly.dly[2].__y : 0 [by t.registers.ack_dly.dly[2]._y:=1] - 401762 t.registers.ack_dly.dly[2].___y : 1 [by t.registers.ack_dly.dly[2].__y:=0] - 401900 t.registers.ack_dly.dly[2].y : 0 [by t.registers.ack_dly.dly[2].___y:=1] - 407163 t.registers.ack_dly.mu2[1]._y : 1 [by t.registers.ack_dly.dly[2].y:=0] - 407165 t.registers._in_a_temp : 0 [by t.registers.ack_dly.mu2[1]._y:=1] - 451082 t.registers.ack_input_X.buf1._y : 1 [by t.registers._in_a_temp:=0] - 451083 t.in.a : 0 [by t.registers.ack_input_X.buf1._y:=1] + 210242 t.dly_cfg[0] : 1 + 210242 t.dly_cfg[1] : 1 + 210243 t.registers.ack_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1] + 210244 t.registers.ack_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1] + 210790 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1] + 254159 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1] + 254170 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0] + 254540 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1] + 254607 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0] + 257248 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1] + 257264 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0] + 261826 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1] + 262354 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0] + 264789 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1] + 291669 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0] + 315594 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1] + 328635 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0] + 328637 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1] + 389595 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0] + 389598 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1] + 389627 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0] + 389944 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1] + 391545 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0] + 391698 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock:=1] + 391742 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0] + 394503 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1] + 408186 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0] + 408187 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1] + 408404 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0] + 408426 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1] + 408427 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0] + 410008 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1] + 419353 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0] + 419512 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1] + 439188 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0] + 440475 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1] + 442707 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0] + 442852 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1] + 445684 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0] + 452038 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1] + 452039 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0] + 491323 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1] + 491485 t.registers._in_a_temp : 1 [by t.registers.ack_dly.mu2[1]._y:=0] + 498854 t.registers.ack_input_X.buf1._y : 0 [by t.registers._in_a_temp:=1] + 498868 t.in.a : 1 [by t.registers.ack_input_X.buf1._y:=0] [2] delay line set - 451083 t.in.d.d[0].t : 1 - 451083 t.in.d.d[4].f : 1 - 451083 t.registers.atree[0].in[0] : 1 - 451083 t.in.d.d[1].t : 1 - 451083 t.registers.atree[0].in[1] : 1 - 451094 t.registers.val_input.OR2_tf[4]._y : 0 [by t.in.d.d[4].f:=1] - 451099 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1] - 451150 t.registers.val_input.OR2_tf[1]._y : 0 [by t.in.d.d[1].t:=1] - 451453 t.registers.val_input.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1] - 451622 t.registers.val_input.ct.in[4] : 1 [by t.registers.val_input.OR2_tf[4]._y:=0] - 451631 t.registers.val_input.OR2_tf[0]._y : 0 [by t.in.d.d[0].t:=1] - 453534 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0] - 453724 t.registers.val_input.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1] - 453726 t.registers.val_input.ct.in[3] : 1 [by t.registers.val_input.OR2_tf[3]._y:=0] - 455645 t.registers.atree[4].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1] - 464672 t.registers.val_input.ct.in[0] : 1 [by t.registers.val_input.OR2_tf[0]._y:=0] - 475378 t.registers.val_input.ct.in[2] : 1 [by t.registers.val_input.OR2_tf[2]._y:=0] - 475381 t.registers.val_input.ct.C3Els[0]._y : 0 [by t.registers.val_input.ct.in[2]:=1] - 475410 t.registers.val_input.ct.tmp[6] : 1 [by t.registers.val_input.ct.C3Els[0]._y:=0] - 478030 t.registers.val_input.ct.in[1] : 1 [by t.registers.val_input.OR2_tf[1]._y:=0] - 478347 t.registers.val_input.ct.C2Els[0]._y : 0 [by t.registers.val_input.ct.in[1]:=1] - 479948 t.registers.val_input.ct.tmp[5] : 1 [by t.registers.val_input.ct.C2Els[0]._y:=0] - 480101 t.registers.val_input.ct.C2Els[1]._y : 0 [by t.registers.val_input.ct.tmp[5]:=1] - 480145 t.registers._in_v_temp : 1 [by t.registers.val_input.ct.C2Els[1]._y:=0] - 482906 t.registers.clk_dly.and2[0]._y : 0 [by t.registers._in_v_temp:=1] - 482907 t.registers.clk_dly.dly[0].a : 1 [by t.registers.clk_dly.and2[0]._y:=0] - 483124 t.registers.clk_dly.dly[0]._y : 0 [by t.registers.clk_dly.dly[0].a:=1] - 483146 t.registers.clk_dly.dly[0].__y : 1 [by t.registers.clk_dly.dly[0]._y:=0] - 483147 t.registers.clk_dly.dly[0].___y : 0 [by t.registers.clk_dly.dly[0].__y:=1] - 484728 t.registers.clk_dly.dly[0].y : 1 [by t.registers.clk_dly.dly[0].___y:=0] - 493828 t.registers.val_input_X.buf1._y : 0 [by t.registers._in_v_temp:=1] - 493987 t.in.v : 1 [by t.registers.val_input_X.buf1._y:=0] - 494073 t.registers.clk_dly.mu2[0]._y : 0 [by t.registers.clk_dly.dly[0].y:=1] - 513749 t.registers.clk_dly._a[1] : 1 [by t.registers.clk_dly.mu2[0]._y:=0] - 515036 t.registers.clk_dly.and2[1]._y : 0 [by t.registers.clk_dly._a[1]:=1] - 516603 t.registers._out_encoder[4] : 1 [by t.registers.atree[4].and2s[0]._y:=0] - 517268 t.registers.clk_dly.dly[1].a : 1 [by t.registers.clk_dly.and2[1]._y:=0] - 517413 t.registers.clk_dly.dly[1]._y : 0 [by t.registers.clk_dly.dly[1].a:=1] - 520245 t.registers.clk_dly.dly[1].__y : 1 [by t.registers.clk_dly.dly[1]._y:=0] - 526599 t.registers.clk_dly.dly[1].___y : 0 [by t.registers.clk_dly.dly[1].__y:=1] - 526600 t.registers.clk_dly.dly[1].y : 1 [by t.registers.clk_dly.dly[1].___y:=0] - 565884 t.registers.clk_dly.dly[2]._y : 0 [by t.registers.clk_dly.dly[1].y:=1] - 566046 t.registers.clk_dly.dly[2].__y : 1 [by t.registers.clk_dly.dly[2]._y:=0] - 573415 t.registers.clk_dly.dly[2].___y : 0 [by t.registers.clk_dly.dly[2].__y:=1] - 573429 t.registers.clk_dly.dly[2].y : 1 [by t.registers.clk_dly.dly[2].___y:=0] - 573436 t.registers.clk_dly.mu2[1]._y : 0 [by t.registers.clk_dly.dly[2].y:=1] - 573596 t.registers._clock_temp : 1 [by t.registers.clk_dly.mu2[1]._y:=0] - 595153 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp:=1] - 595154 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0] - 595155 t.registers.and_encoder[4]._y : 0 [by t.registers._clock:=1] - 595155 t.registers.and_encoder[0]._y : 0 [by t.registers._clock:=1] - 595156 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0] - 595342 t.registers._clock_word_temp[4] : 1 [by t.registers.and_encoder[4]._y:=0] - 597397 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock:=1] - 597398 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0] - 598251 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1] - 598256 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0] - 599147 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1] - 599148 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0] - 599165 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1] -WARNING: interference `t.registers._clock_buffer_out[0]' ->> cause: t.registers.clock_buffer[0].buf1._y (val: 0) ->> time: 599338 - 599338 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1] - 601738 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0] - 601741 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1] - 602682 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0] - 607699 t.registers._clock_buffer_out[0] : X [by t.registers.clock_buffer[0].buf1._y:=0] - 630124 t.registers.clock_buffer[4].buf1._y : 0 [by t.registers._clock_word_temp[4]:=1] - 661644 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1] - 661645 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0] - 661687 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1] - 664504 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0] - 678237 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1] - 678332 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0] - 678667 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1] - 678675 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0] - 678709 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1] - 692596 t.registers._in_a_temp : 1 [by t.registers.ack_dly.mu2[1]._y:=0] - 693514 t.registers.ack_input_X.buf1._y : 0 [by t.registers._in_a_temp:=1] - 693518 t.in.a : 1 [by t.registers.ack_input_X.buf1._y:=0] - 693518 t.in.d.d[0].t : 0 - 693518 t.in.d.d[4].f : 0 - 693518 t.registers.atree[0].in[0] : 0 - 693518 t.in.d.d[1].t : 0 - 693518 t.registers.atree[0].in[1] : 0 - 693521 t.registers.val_input.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0] - 693566 t.registers.atree[4].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0] - 693696 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0] - 695916 t.registers.val_input.OR2_tf[4]._y : 1 [by t.in.d.d[4].f:=0] - 696733 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] - 697560 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1] - 699647 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1] - 705465 t.registers._out_encoder[4] : 0 [by t.registers.atree[4].and2s[0]._y:=1] - 705638 t.registers.and_encoder[4]._y : 1 [by t.registers._out_encoder[4]:=0] - 705822 t.registers._clock_word_temp[4] : 0 [by t.registers.and_encoder[4]._y:=1] - 705823 t.registers.clock_buffer[4].buf1._y : 1 [by t.registers._clock_word_temp[4]:=0] - 714498 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1] - 735401 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1] - 735474 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[4]:=0] - 735478 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1] - 739896 t.registers.val_input.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0] - 740637 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0] - 740733 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] - 740869 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0] - 740870 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] - 759916 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] - 760157 t.registers._clock_buffer_out[0] : 0 [by t.registers.clock_buffer[0].buf1._y:=1] - 777184 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1] - 781143 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[0]:=0] - 781155 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1] - 785055 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[5]:=0] - 786084 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1] - 786085 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp:=0] - 786140 t.registers.val_input_X.buf1._y : 1 [by t.registers._in_v_temp:=0] - 786141 t.in.v : 0 [by t.registers.val_input_X.buf1._y:=1] - 831091 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1] - 831128 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0] - 854503 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1] - 854504 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0] - 858068 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1] - 859760 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.dly[0].y:=0] - 859773 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1] - 876757 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0] - 877114 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1] - 877139 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0] - 877160 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1] - 877161 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0] - 886809 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1] - 886810 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0] - 886811 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1] - 886972 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0] - 888009 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1] - 888014 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0] - 888595 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1] - 889003 t.registers.clk_X.buf1._y : 1 [by t.registers._clock_temp:=0] - 889014 t.registers._clock : 0 [by t.registers.clk_X.buf1._y:=1] - 890061 t.registers.ack_dly.and2[0]._y : 1 [by t.registers._clock:=0] - 890075 t.registers.ack_dly.dly[0].a : 0 [by t.registers.ack_dly.and2[0]._y:=1] - 890093 t.registers.ack_dly.dly[0]._y : 1 [by t.registers.ack_dly.dly[0].a:=0] - 890097 t.registers.ack_dly.dly[0].__y : 0 [by t.registers.ack_dly.dly[0]._y:=1] - 890201 t.registers.ack_dly.dly[0].___y : 1 [by t.registers.ack_dly.dly[0].__y:=0] - 921645 t.registers.ack_dly.dly[0].y : 0 [by t.registers.ack_dly.dly[0].___y:=1] - 922849 t.registers.ack_dly.mu2[0]._y : 1 [by t.registers.ack_dly.dly[0].y:=0] - 931304 t.registers.ack_dly._a[1] : 0 [by t.registers.ack_dly.mu2[0]._y:=1] - 931532 t.registers.ack_dly.and2[1]._y : 1 [by t.registers.ack_dly._a[1]:=0] - 932375 t.registers.ack_dly.dly[1].a : 0 [by t.registers.ack_dly.and2[1]._y:=1] - 933834 t.registers.ack_dly.dly[1]._y : 1 [by t.registers.ack_dly.dly[1].a:=0] - 933904 t.registers.ack_dly.dly[1].__y : 0 [by t.registers.ack_dly.dly[1]._y:=1] - 984326 t.registers.ack_dly.dly[1].___y : 1 [by t.registers.ack_dly.dly[1].__y:=0] - 984337 t.registers.ack_dly.dly[1].y : 0 [by t.registers.ack_dly.dly[1].___y:=1] - 984340 t.registers.ack_dly.dly[2]._y : 1 [by t.registers.ack_dly.dly[1].y:=0] - 984394 t.registers.ack_dly.dly[2].__y : 0 [by t.registers.ack_dly.dly[2]._y:=1] - 985542 t.registers.ack_dly.dly[2].___y : 1 [by t.registers.ack_dly.dly[2].__y:=0] - 986703 t.registers.ack_dly.dly[2].y : 0 [by t.registers.ack_dly.dly[2].___y:=1] - 995355 t.registers.ack_dly.mu2[1]._y : 1 [by t.registers.ack_dly.dly[2].y:=0] - 995436 t.registers._in_a_temp : 0 [by t.registers.ack_dly.mu2[1]._y:=1] - 1006513 t.registers.ack_input_X.buf1._y : 1 [by t.registers._in_a_temp:=0] - 1024496 t.in.a : 0 [by t.registers.ack_input_X.buf1._y:=1] -WRONG ASSERT: "t.registers.ff[0].q" has value X and not 1. -WRONG ASSERT: "t.registers.ff[1].q" has value X and not 1. + 498868 t.registers.ff[0].d : 1 + 498868 t.in.d.d[4].f : 1 + 498868 t.registers.atree[0].in[0] : 1 + 498868 t.registers.ff[1].d : 1 + 498868 t.registers.atree[0].in[1] : 1 + 498869 t.registers.val_input.OR2_tf[1]._y : 0 [by t.registers.ff[1].d:=1] + 498869 t.registers.val_input.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1] + 498869 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1] + 498870 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0] + 498875 t.registers.val_input.OR2_tf[0]._y : 0 [by t.registers.ff[0].d:=1] + 499028 t.registers.val_input.OR2_tf[4]._y : 0 [by t.in.d.d[4].f:=1] + 499029 t.registers.val_input.ct.in[4] : 1 [by t.registers.val_input.OR2_tf[4]._y:=0] + 499056 t.registers.val_input.ct.in[3] : 1 [by t.registers.val_input.OR2_tf[3]._y:=0] + 501112 t.registers.val_input.ct.in[1] : 1 [by t.registers.val_input.OR2_tf[1]._y:=0] + 503052 t.registers.and_encoder[0]._y : 0 [by t.registers._out_encoder[0]:=1] + 503905 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0] + 503910 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1] + 504801 t.registers.ff[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0] + 504802 t.registers.ff[0]._clk_B : 0 [by t.registers.ff[0].clk_B:=1] + 504818 t.registers.ff[1]._clk_B : 0 [by t.registers.ff[0].clk_B:=1] + 507375 t.registers.ff[0].__clk_B : 1 [by t.registers.ff[0]._clk_B:=0] + 507378 t.registers.ff[0]._mqib : 0 [by t.registers.ff[0].__clk_B:=1] + 508319 t.registers.ff[0]._mqi : 1 [by t.registers.ff[0]._mqib:=0] + 513179 t.registers.ff[1].__clk_B : 1 [by t.registers.ff[1]._clk_B:=0] + 520425 t.registers.val_input.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1] + 520426 t.registers.val_input.ct.in[2] : 1 [by t.registers.val_input.OR2_tf[2]._y:=0] + 520468 t.registers.val_input.ct.C3Els[0]._y : 0 [by t.registers.val_input.ct.in[2]:=1] + 523285 t.registers.val_input.ct.tmp[6] : 1 [by t.registers.val_input.ct.C3Els[0]._y:=0] + 533657 t.registers.val_input.ct.in[0] : 1 [by t.registers.val_input.OR2_tf[0]._y:=0] + 547390 t.registers.val_input.ct.C2Els[0]._y : 0 [by t.registers.val_input.ct.in[0]:=1] + 547485 t.registers.val_input.ct.tmp[5] : 1 [by t.registers.val_input.ct.C2Els[0]._y:=0] + 547820 t.registers.val_input.ct.C2Els[1]._y : 0 [by t.registers.val_input.ct.tmp[5]:=1] + 547828 t.registers._in_v_temp : 1 [by t.registers.val_input.ct.C2Els[1]._y:=0] + 547862 t.registers.clk_dly.and2[0]._y : 0 [by t.registers._in_v_temp:=1] + 548780 t.registers.clk_dly.dly[0].a : 1 [by t.registers.clk_dly.and2[0]._y:=0] + 548784 t.registers.clk_dly.dly[0]._y : 0 [by t.registers.clk_dly.dly[0].a:=1] + 561715 t.registers.val_input_X.buf1._y : 0 [by t.registers._in_v_temp:=1] + 564113 t.in.v : 1 [by t.registers.val_input_X.buf1._y:=0] + 572141 t.registers.ff[1]._mqib : 0 [by t.registers.ff[1].__clk_B:=1] + 575356 t.registers.ff[1]._mqi : 1 [by t.registers.ff[1]._mqib:=0] + 595162 t.registers.clk_dly.dly[0].__y : 1 [by t.registers.clk_dly.dly[0]._y:=0] + 642281 t.registers.clk_dly.dly[0].___y : 0 [by t.registers.clk_dly.dly[0].__y:=1] + 642329 t.registers.clk_dly.dly[0].y : 1 [by t.registers.clk_dly.dly[0].___y:=0] + 642332 t.registers.clk_dly.mu2[0]._y : 0 [by t.registers.clk_dly.dly[0].y:=1] + 642510 t.registers.clk_dly._a[1] : 1 [by t.registers.clk_dly.mu2[0]._y:=0] + 663487 t.registers.clk_dly.and2[1]._y : 0 [by t.registers.clk_dly._a[1]:=1] + 675386 t.registers.clk_dly.dly[1].a : 1 [by t.registers.clk_dly.and2[1]._y:=0] + 681337 t.registers.clk_dly.dly[1]._y : 0 [by t.registers.clk_dly.dly[1].a:=1] + 720822 t.registers.clk_dly.dly[1].__y : 1 [by t.registers.clk_dly.dly[1]._y:=0] + 721649 t.registers.clk_dly.dly[1].___y : 0 [by t.registers.clk_dly.dly[1].__y:=1] + 721822 t.registers.clk_dly.dly[1].y : 1 [by t.registers.clk_dly.dly[1].___y:=0] + 722006 t.registers.clk_dly.dly[2]._y : 0 [by t.registers.clk_dly.dly[1].y:=1] + 722007 t.registers.clk_dly.dly[2].__y : 1 [by t.registers.clk_dly.dly[2]._y:=0] + 722080 t.registers.clk_dly.dly[2].___y : 0 [by t.registers.clk_dly.dly[2].__y:=1] + 722084 t.registers.clk_dly.dly[2].y : 1 [by t.registers.clk_dly.dly[2].___y:=0] + 759372 t.registers.clk_dly.mu2[1]._y : 0 [by t.registers.clk_dly.dly[2].y:=1] + 759468 t.registers._clock_temp : 1 [by t.registers.clk_dly.mu2[1]._y:=0] + 759604 t.registers._clock_temp_inv : 0 [by t.registers._clock_temp:=1] + 759605 t.registers.clk_X.buf1._y : 1 [by t.registers._clock_temp_inv:=0] + 778651 t.registers._clock : 0 [by t.registers.clk_X.buf1._y:=1] + 778892 t.registers.and_encoder[0]._y : 1 [by t.registers._clock:=0] + 778904 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1] + 782610 t.registers.ack_dly.and2[0]._y : 1 [by t.registers._clock:=0] + 782804 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0] + 782805 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1] + 782861 t.registers.ff[0]._clk_B : 1 [by t.registers.ff[0].clk_B:=0] + 782862 t.registers.ff[0].__clk_B : 0 [by t.registers.ff[0]._clk_B:=1] + 782898 t.registers.ff[0]._sqib : 0 [by t.registers.ff[0]._clk_B:=1] + 782899 t.data[0].d[0] : 1 [by t.registers.ff[0]._sqib:=0] + 783639 t.registers.ack_dly.dly[0].a : 0 [by t.registers.ack_dly.and2[0]._y:=1] + 787203 t.registers.ack_dly.dly[0]._y : 1 [by t.registers.ack_dly.dly[0].a:=0] + 788895 t.registers.ack_dly.dly[0].__y : 0 [by t.registers.ack_dly.dly[0]._y:=1] + 788908 t.registers.ack_dly.dly[0].___y : 1 [by t.registers.ack_dly.dly[0].__y:=0] + 805892 t.registers.ack_dly.dly[0].y : 0 [by t.registers.ack_dly.dly[0].___y:=1] + 806249 t.registers.ack_dly.mu2[0]._y : 1 [by t.registers.ack_dly.dly[0].y:=0] + 806273 t.registers.ff[0]._sqi : 1 [by t.registers.ff[0]._sqib:=0] + 806274 t.registers.ack_dly._a[1] : 0 [by t.registers.ack_dly.mu2[0]._y:=1] + 806295 t.registers.ack_dly.and2[1]._y : 1 [by t.registers.ack_dly._a[1]:=0] + 806296 t.registers.ack_dly.dly[1].a : 0 [by t.registers.ack_dly.and2[1]._y:=1] + 815944 t.registers.ack_dly.dly[1]._y : 1 [by t.registers.ack_dly.dly[1].a:=0] + 815945 t.registers.ack_dly.dly[1].__y : 0 [by t.registers.ack_dly.dly[1]._y:=1] + 815946 t.registers.ack_dly.dly[1].___y : 1 [by t.registers.ack_dly.dly[1].__y:=0] + 816107 t.registers.ack_dly.dly[1].y : 0 [by t.registers.ack_dly.dly[1].___y:=1] + 817144 t.registers.ack_dly.dly[2]._y : 1 [by t.registers.ack_dly.dly[1].y:=0] + 817149 t.registers.ack_dly.dly[2].__y : 0 [by t.registers.ack_dly.dly[2]._y:=1] + 817730 t.registers.ack_dly.dly[2].___y : 1 [by t.registers.ack_dly.dly[2].__y:=0] + 818138 t.registers.ack_dly.dly[2].y : 0 [by t.registers.ack_dly.dly[2].___y:=1] + 818149 t.registers.ack_dly.mu2[1]._y : 1 [by t.registers.ack_dly.dly[2].y:=0] + 819196 t.registers._in_a_temp : 0 [by t.registers.ack_dly.mu2[1]._y:=1] + 819210 t.registers.ack_input_X.buf1._y : 1 [by t.registers._in_a_temp:=0] + 819228 t.in.a : 0 [by t.registers.ack_input_X.buf1._y:=1] + 827811 t.registers.ff[1]._clk_B : 1 [by t.registers.ff[0].clk_B:=0] + 827815 t.registers.ff[1].__clk_B : 0 [by t.registers.ff[1]._clk_B:=1] + 827915 t.registers.ff[1]._sqib : 0 [by t.registers.ff[1]._clk_B:=1] + 829119 t.data[0].d[1] : 1 [by t.registers.ff[1]._sqib:=0] + 859359 t.registers.ff[1]._sqi : 1 [by t.registers.ff[1]._sqib:=0] + 859359 t.registers.ff[0].d : 0 + 859359 t.in.d.d[4].f : 0 + 859359 t.registers.atree[0].in[0] : 0 + 859359 t.registers.ff[1].d : 0 + 859359 t.registers.atree[0].in[1] : 0 + 859429 t.registers.val_input.OR2_tf[1]._y : 1 [by t.registers.ff[1].d:=0] + 859440 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1] + 859587 t.registers.val_input.OR2_tf[4]._y : 1 [by t.in.d.d[4].f:=0] + 859590 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1] + 860202 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0] + 860256 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1] + 860818 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0] + 861966 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1] + 867814 t.registers.val_input.OR2_tf[0]._y : 1 [by t.registers.ff[0].d:=0] + 868975 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1] + 877627 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[0]:=0] + 877708 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1] + 909781 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0] + 920858 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1] + 938841 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[3]:=0] + 938933 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1] + 947244 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[6]:=0] + 948988 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1] + 949601 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp:=0] + 949646 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1] + 950643 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0] + 952292 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1] + 952817 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0] + 953717 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1] + 953769 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.dly[0].y:=0] + 953776 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1] + 963010 t.registers.val_input_X.buf1._y : 1 [by t.registers._in_v_temp:=0] + 969388 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0] + 969390 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1] + 969477 t.in.v : 0 [by t.registers.val_input_X.buf1._y:=1] + 969744 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0] + 969877 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1] + 969878 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0] + 969882 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1] + 970428 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0] + 1015991 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1] + 1015992 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0] + 1028370 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1] + 1028449 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0] + 1030882 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1] + 1030970 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0] + 1038752 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1] + 1067079 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0] + 1067138 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock:=1] + 1067168 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0] + 1068635 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1] + 1128139 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0] + 1147523 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1] + 1148208 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0] + 1164923 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1] + 1165050 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0] + 1165219 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1] + 1165262 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0] + 1165274 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1] + 1166553 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0] + 1166786 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1] + 1166789 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0] + 1166827 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1] + 1166828 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0] + 1179580 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1] + 1179672 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0] + 1182399 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1] + 1182401 t.registers._in_a_temp : 1 [by t.registers.ack_dly.mu2[1]._y:=0] + 1182402 t.registers.ack_input_X.buf1._y : 0 [by t.registers._in_a_temp:=1] + 1183903 t.in.a : 1 [by t.registers.ack_input_X.buf1._y:=0] [3] clock checked diff --git a/test/unit_tests/register_write/run/test.prs b/test/unit_tests/register_write/run/test.prs index b663a6e..34a2845 100644 --- a/test/unit_tests/register_write/run/test.prs +++ b/test/unit_tests/register_write/run/test.prs @@ -13,34 +13,18 @@ = "t.data[1].d[0]" "t.registers.data[1].d[0]" = "t.data[2].d[0]" "t.registers.data[2].d[0]" = "t.data[3].d[0]" "t.registers.data[3].d[0]" -= "t.data[4].d[0]" "t.registers.data[4].d[0]" -= "t.data[5].d[0]" "t.registers.data[5].d[0]" -= "t.data[6].d[0]" "t.registers.data[6].d[0]" -= "t.data[7].d[0]" "t.registers.data[7].d[0]" = "t.data[0].d[1]" "t.registers.data[0].d[1]" = "t.data[1].d[1]" "t.registers.data[1].d[1]" = "t.data[2].d[1]" "t.registers.data[2].d[1]" = "t.data[3].d[1]" "t.registers.data[3].d[1]" -= "t.data[4].d[1]" "t.registers.data[4].d[1]" -= "t.data[5].d[1]" "t.registers.data[5].d[1]" -= "t.data[6].d[1]" "t.registers.data[6].d[1]" -= "t.data[7].d[1]" "t.registers.data[7].d[1]" -= "t.registers._clock_temp" "t.registers.clk_X.in" += "t.registers._clock_temp" "t.registers.inv_clk.a" = "t.registers._clock_temp" "t.registers.clk_dly.out" -"t.registers.reset_bufarray.buf6.a"->"t.registers.reset_bufarray.buf6._y"- -~("t.registers.reset_bufarray.buf6.a")->"t.registers.reset_bufarray.buf6._y"+ -"t.registers.reset_bufarray.buf6._y"->"t.registers.reset_bufarray.buf6.y"- -~("t.registers.reset_bufarray.buf6._y")->"t.registers.reset_bufarray.buf6.y"+ -= "t.registers.reset_bufarray.supply.vdd" "t.registers.reset_bufarray.buf6.vdd" -= "t.registers.reset_bufarray.supply.vss" "t.registers.reset_bufarray.buf6.vss" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[15]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[14]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[13]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[12]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[11]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[10]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[9]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[8]" +"t.registers.reset_bufarray.buf3.a"->"t.registers.reset_bufarray.buf3._y"- +~("t.registers.reset_bufarray.buf3.a")->"t.registers.reset_bufarray.buf3._y"+ +"t.registers.reset_bufarray.buf3._y"->"t.registers.reset_bufarray.buf3.y"- +~("t.registers.reset_bufarray.buf3._y")->"t.registers.reset_bufarray.buf3.y"+ += "t.registers.reset_bufarray.supply.vdd" "t.registers.reset_bufarray.buf3.vdd" += "t.registers.reset_bufarray.supply.vss" "t.registers.reset_bufarray.buf3.vss" = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[7]" = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[6]" = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[5]" @@ -48,232 +32,134 @@ = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[3]" = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[2]" = "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[1]" -= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.buf6.y" -= "t.registers.reset_bufarray.in" "t.registers.reset_bufarray.buf6.a" -"t.registers.ff[0].clk"->"t.registers.ff[0]._clk"- -~("t.registers.ff[0].clk")->"t.registers.ff[0]._clk"+ -"t.registers.ff[0]._clk"->"t.registers.ff[0].__clk"- -~("t.registers.ff[0]._clk")->"t.registers.ff[0].__clk"+ -~"t.registers.ff[0].d"&~"t.registers.ff[0]._clk"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0].__clk"&~"t.registers.ff[0]._mqi"->"t.registers.ff[0]._mqib"+ -"t.registers.ff[0].d"&"t.registers.ff[0].__clk"|"t.registers.ff[0].reset_B"&"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk"->"t.registers.ff[0]._mqib"- += "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.buf3.y" += "t.registers.reset_bufarray.in" "t.registers.reset_bufarray.buf3.a" +"t.registers.ff[0].clk_B"->"t.registers.ff[0]._clk_B"- +~("t.registers.ff[0].clk_B")->"t.registers.ff[0]._clk_B"+ +"t.registers.ff[0]._clk_B"->"t.registers.ff[0].__clk_B"- +~("t.registers.ff[0]._clk_B")->"t.registers.ff[0].__clk_B"+ +~"t.registers.ff[0].d"&~"t.registers.ff[0]._clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0].__clk_B"&~"t.registers.ff[0]._mqi"->"t.registers.ff[0]._mqib"+ +("t.registers.ff[0].d"&"t.registers.ff[0].__clk_B"|"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._mqib"- "t.registers.ff[0]._mqib"->"t.registers.ff[0]._mqi"- ~("t.registers.ff[0]._mqib")->"t.registers.ff[0]._mqi"+ -~"t.registers.ff[0]._mqi"&~"t.registers.ff[0].__clk"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0]._sqi"&~"t.registers.ff[0]._clk"->"t.registers.ff[0]._sqib"+ -"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk"|"t.registers.ff[0]._sqi"&"t.registers.ff[0].__clk"&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._sqib"- +~"t.registers.ff[0]._mqi"&~"t.registers.ff[0].__clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0]._sqi"&~"t.registers.ff[0]._clk_B"->"t.registers.ff[0]._sqib"+ +("t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B"|"t.registers.ff[0]._sqi"&"t.registers.ff[0].__clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._sqib"- "t.registers.ff[0]._sqib"->"t.registers.ff[0]._sqi"- ~("t.registers.ff[0]._sqib")->"t.registers.ff[0]._sqi"+ "t.registers.ff[0]._sqib"->"t.registers.ff[0].q"- ~("t.registers.ff[0]._sqib")->"t.registers.ff[0].q"+ -"t.registers.ff[1].clk"->"t.registers.ff[1]._clk"- -~("t.registers.ff[1].clk")->"t.registers.ff[1]._clk"+ -"t.registers.ff[1]._clk"->"t.registers.ff[1].__clk"- -~("t.registers.ff[1]._clk")->"t.registers.ff[1].__clk"+ -~"t.registers.ff[1].d"&~"t.registers.ff[1]._clk"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1].__clk"&~"t.registers.ff[1]._mqi"->"t.registers.ff[1]._mqib"+ -"t.registers.ff[1].d"&"t.registers.ff[1].__clk"|"t.registers.ff[1].reset_B"&"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk"->"t.registers.ff[1]._mqib"- +"t.registers.ff[1].clk_B"->"t.registers.ff[1]._clk_B"- +~("t.registers.ff[1].clk_B")->"t.registers.ff[1]._clk_B"+ +"t.registers.ff[1]._clk_B"->"t.registers.ff[1].__clk_B"- +~("t.registers.ff[1]._clk_B")->"t.registers.ff[1].__clk_B"+ +~"t.registers.ff[1].d"&~"t.registers.ff[1]._clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1].__clk_B"&~"t.registers.ff[1]._mqi"->"t.registers.ff[1]._mqib"+ +("t.registers.ff[1].d"&"t.registers.ff[1].__clk_B"|"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._mqib"- "t.registers.ff[1]._mqib"->"t.registers.ff[1]._mqi"- ~("t.registers.ff[1]._mqib")->"t.registers.ff[1]._mqi"+ -~"t.registers.ff[1]._mqi"&~"t.registers.ff[1].__clk"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1]._sqi"&~"t.registers.ff[1]._clk"->"t.registers.ff[1]._sqib"+ -"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk"|"t.registers.ff[1]._sqi"&"t.registers.ff[1].__clk"&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._sqib"- +~"t.registers.ff[1]._mqi"&~"t.registers.ff[1].__clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1]._sqi"&~"t.registers.ff[1]._clk_B"->"t.registers.ff[1]._sqib"+ +("t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B"|"t.registers.ff[1]._sqi"&"t.registers.ff[1].__clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._sqib"- "t.registers.ff[1]._sqib"->"t.registers.ff[1]._sqi"- ~("t.registers.ff[1]._sqib")->"t.registers.ff[1]._sqi"+ "t.registers.ff[1]._sqib"->"t.registers.ff[1].q"- ~("t.registers.ff[1]._sqib")->"t.registers.ff[1].q"+ -"t.registers.ff[2].clk"->"t.registers.ff[2]._clk"- -~("t.registers.ff[2].clk")->"t.registers.ff[2]._clk"+ -"t.registers.ff[2]._clk"->"t.registers.ff[2].__clk"- -~("t.registers.ff[2]._clk")->"t.registers.ff[2].__clk"+ -~"t.registers.ff[2].d"&~"t.registers.ff[2]._clk"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2].__clk"&~"t.registers.ff[2]._mqi"->"t.registers.ff[2]._mqib"+ -"t.registers.ff[2].d"&"t.registers.ff[2].__clk"|"t.registers.ff[2].reset_B"&"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk"->"t.registers.ff[2]._mqib"- +"t.registers.ff[2].clk_B"->"t.registers.ff[2]._clk_B"- +~("t.registers.ff[2].clk_B")->"t.registers.ff[2]._clk_B"+ +"t.registers.ff[2]._clk_B"->"t.registers.ff[2].__clk_B"- +~("t.registers.ff[2]._clk_B")->"t.registers.ff[2].__clk_B"+ +~"t.registers.ff[2].d"&~"t.registers.ff[2]._clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2].__clk_B"&~"t.registers.ff[2]._mqi"->"t.registers.ff[2]._mqib"+ +("t.registers.ff[2].d"&"t.registers.ff[2].__clk_B"|"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._mqib"- "t.registers.ff[2]._mqib"->"t.registers.ff[2]._mqi"- ~("t.registers.ff[2]._mqib")->"t.registers.ff[2]._mqi"+ -~"t.registers.ff[2]._mqi"&~"t.registers.ff[2].__clk"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2]._sqi"&~"t.registers.ff[2]._clk"->"t.registers.ff[2]._sqib"+ -"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk"|"t.registers.ff[2]._sqi"&"t.registers.ff[2].__clk"&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._sqib"- +~"t.registers.ff[2]._mqi"&~"t.registers.ff[2].__clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2]._sqi"&~"t.registers.ff[2]._clk_B"->"t.registers.ff[2]._sqib"+ +("t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B"|"t.registers.ff[2]._sqi"&"t.registers.ff[2].__clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._sqib"- "t.registers.ff[2]._sqib"->"t.registers.ff[2]._sqi"- ~("t.registers.ff[2]._sqib")->"t.registers.ff[2]._sqi"+ "t.registers.ff[2]._sqib"->"t.registers.ff[2].q"- ~("t.registers.ff[2]._sqib")->"t.registers.ff[2].q"+ -"t.registers.ff[3].clk"->"t.registers.ff[3]._clk"- -~("t.registers.ff[3].clk")->"t.registers.ff[3]._clk"+ -"t.registers.ff[3]._clk"->"t.registers.ff[3].__clk"- -~("t.registers.ff[3]._clk")->"t.registers.ff[3].__clk"+ -~"t.registers.ff[3].d"&~"t.registers.ff[3]._clk"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3].__clk"&~"t.registers.ff[3]._mqi"->"t.registers.ff[3]._mqib"+ -"t.registers.ff[3].d"&"t.registers.ff[3].__clk"|"t.registers.ff[3].reset_B"&"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk"->"t.registers.ff[3]._mqib"- +"t.registers.ff[3].clk_B"->"t.registers.ff[3]._clk_B"- +~("t.registers.ff[3].clk_B")->"t.registers.ff[3]._clk_B"+ +"t.registers.ff[3]._clk_B"->"t.registers.ff[3].__clk_B"- +~("t.registers.ff[3]._clk_B")->"t.registers.ff[3].__clk_B"+ +~"t.registers.ff[3].d"&~"t.registers.ff[3]._clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3].__clk_B"&~"t.registers.ff[3]._mqi"->"t.registers.ff[3]._mqib"+ +("t.registers.ff[3].d"&"t.registers.ff[3].__clk_B"|"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._mqib"- "t.registers.ff[3]._mqib"->"t.registers.ff[3]._mqi"- ~("t.registers.ff[3]._mqib")->"t.registers.ff[3]._mqi"+ -~"t.registers.ff[3]._mqi"&~"t.registers.ff[3].__clk"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3]._sqi"&~"t.registers.ff[3]._clk"->"t.registers.ff[3]._sqib"+ -"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk"|"t.registers.ff[3]._sqi"&"t.registers.ff[3].__clk"&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._sqib"- +~"t.registers.ff[3]._mqi"&~"t.registers.ff[3].__clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3]._sqi"&~"t.registers.ff[3]._clk_B"->"t.registers.ff[3]._sqib"+ +("t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B"|"t.registers.ff[3]._sqi"&"t.registers.ff[3].__clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._sqib"- "t.registers.ff[3]._sqib"->"t.registers.ff[3]._sqi"- ~("t.registers.ff[3]._sqib")->"t.registers.ff[3]._sqi"+ "t.registers.ff[3]._sqib"->"t.registers.ff[3].q"- ~("t.registers.ff[3]._sqib")->"t.registers.ff[3].q"+ -"t.registers.ff[4].clk"->"t.registers.ff[4]._clk"- -~("t.registers.ff[4].clk")->"t.registers.ff[4]._clk"+ -"t.registers.ff[4]._clk"->"t.registers.ff[4].__clk"- -~("t.registers.ff[4]._clk")->"t.registers.ff[4].__clk"+ -~"t.registers.ff[4].d"&~"t.registers.ff[4]._clk"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4].__clk"&~"t.registers.ff[4]._mqi"->"t.registers.ff[4]._mqib"+ -"t.registers.ff[4].d"&"t.registers.ff[4].__clk"|"t.registers.ff[4].reset_B"&"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk"->"t.registers.ff[4]._mqib"- +"t.registers.ff[4].clk_B"->"t.registers.ff[4]._clk_B"- +~("t.registers.ff[4].clk_B")->"t.registers.ff[4]._clk_B"+ +"t.registers.ff[4]._clk_B"->"t.registers.ff[4].__clk_B"- +~("t.registers.ff[4]._clk_B")->"t.registers.ff[4].__clk_B"+ +~"t.registers.ff[4].d"&~"t.registers.ff[4]._clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4].__clk_B"&~"t.registers.ff[4]._mqi"->"t.registers.ff[4]._mqib"+ +("t.registers.ff[4].d"&"t.registers.ff[4].__clk_B"|"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._mqib"- "t.registers.ff[4]._mqib"->"t.registers.ff[4]._mqi"- ~("t.registers.ff[4]._mqib")->"t.registers.ff[4]._mqi"+ -~"t.registers.ff[4]._mqi"&~"t.registers.ff[4].__clk"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4]._sqi"&~"t.registers.ff[4]._clk"->"t.registers.ff[4]._sqib"+ -"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk"|"t.registers.ff[4]._sqi"&"t.registers.ff[4].__clk"&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._sqib"- +~"t.registers.ff[4]._mqi"&~"t.registers.ff[4].__clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4]._sqi"&~"t.registers.ff[4]._clk_B"->"t.registers.ff[4]._sqib"+ +("t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B"|"t.registers.ff[4]._sqi"&"t.registers.ff[4].__clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._sqib"- "t.registers.ff[4]._sqib"->"t.registers.ff[4]._sqi"- ~("t.registers.ff[4]._sqib")->"t.registers.ff[4]._sqi"+ "t.registers.ff[4]._sqib"->"t.registers.ff[4].q"- ~("t.registers.ff[4]._sqib")->"t.registers.ff[4].q"+ -"t.registers.ff[5].clk"->"t.registers.ff[5]._clk"- -~("t.registers.ff[5].clk")->"t.registers.ff[5]._clk"+ -"t.registers.ff[5]._clk"->"t.registers.ff[5].__clk"- -~("t.registers.ff[5]._clk")->"t.registers.ff[5].__clk"+ -~"t.registers.ff[5].d"&~"t.registers.ff[5]._clk"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5].__clk"&~"t.registers.ff[5]._mqi"->"t.registers.ff[5]._mqib"+ -"t.registers.ff[5].d"&"t.registers.ff[5].__clk"|"t.registers.ff[5].reset_B"&"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk"->"t.registers.ff[5]._mqib"- +"t.registers.ff[5].clk_B"->"t.registers.ff[5]._clk_B"- +~("t.registers.ff[5].clk_B")->"t.registers.ff[5]._clk_B"+ +"t.registers.ff[5]._clk_B"->"t.registers.ff[5].__clk_B"- +~("t.registers.ff[5]._clk_B")->"t.registers.ff[5].__clk_B"+ +~"t.registers.ff[5].d"&~"t.registers.ff[5]._clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5].__clk_B"&~"t.registers.ff[5]._mqi"->"t.registers.ff[5]._mqib"+ +("t.registers.ff[5].d"&"t.registers.ff[5].__clk_B"|"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._mqib"- "t.registers.ff[5]._mqib"->"t.registers.ff[5]._mqi"- ~("t.registers.ff[5]._mqib")->"t.registers.ff[5]._mqi"+ -~"t.registers.ff[5]._mqi"&~"t.registers.ff[5].__clk"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5]._sqi"&~"t.registers.ff[5]._clk"->"t.registers.ff[5]._sqib"+ -"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk"|"t.registers.ff[5]._sqi"&"t.registers.ff[5].__clk"&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._sqib"- +~"t.registers.ff[5]._mqi"&~"t.registers.ff[5].__clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5]._sqi"&~"t.registers.ff[5]._clk_B"->"t.registers.ff[5]._sqib"+ +("t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B"|"t.registers.ff[5]._sqi"&"t.registers.ff[5].__clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._sqib"- "t.registers.ff[5]._sqib"->"t.registers.ff[5]._sqi"- ~("t.registers.ff[5]._sqib")->"t.registers.ff[5]._sqi"+ "t.registers.ff[5]._sqib"->"t.registers.ff[5].q"- ~("t.registers.ff[5]._sqib")->"t.registers.ff[5].q"+ -"t.registers.ff[6].clk"->"t.registers.ff[6]._clk"- -~("t.registers.ff[6].clk")->"t.registers.ff[6]._clk"+ -"t.registers.ff[6]._clk"->"t.registers.ff[6].__clk"- -~("t.registers.ff[6]._clk")->"t.registers.ff[6].__clk"+ -~"t.registers.ff[6].d"&~"t.registers.ff[6]._clk"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6].__clk"&~"t.registers.ff[6]._mqi"->"t.registers.ff[6]._mqib"+ -"t.registers.ff[6].d"&"t.registers.ff[6].__clk"|"t.registers.ff[6].reset_B"&"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk"->"t.registers.ff[6]._mqib"- +"t.registers.ff[6].clk_B"->"t.registers.ff[6]._clk_B"- +~("t.registers.ff[6].clk_B")->"t.registers.ff[6]._clk_B"+ +"t.registers.ff[6]._clk_B"->"t.registers.ff[6].__clk_B"- +~("t.registers.ff[6]._clk_B")->"t.registers.ff[6].__clk_B"+ +~"t.registers.ff[6].d"&~"t.registers.ff[6]._clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6].__clk_B"&~"t.registers.ff[6]._mqi"->"t.registers.ff[6]._mqib"+ +("t.registers.ff[6].d"&"t.registers.ff[6].__clk_B"|"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._mqib"- "t.registers.ff[6]._mqib"->"t.registers.ff[6]._mqi"- ~("t.registers.ff[6]._mqib")->"t.registers.ff[6]._mqi"+ -~"t.registers.ff[6]._mqi"&~"t.registers.ff[6].__clk"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6]._sqi"&~"t.registers.ff[6]._clk"->"t.registers.ff[6]._sqib"+ -"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk"|"t.registers.ff[6]._sqi"&"t.registers.ff[6].__clk"&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._sqib"- +~"t.registers.ff[6]._mqi"&~"t.registers.ff[6].__clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6]._sqi"&~"t.registers.ff[6]._clk_B"->"t.registers.ff[6]._sqib"+ +("t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B"|"t.registers.ff[6]._sqi"&"t.registers.ff[6].__clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._sqib"- "t.registers.ff[6]._sqib"->"t.registers.ff[6]._sqi"- ~("t.registers.ff[6]._sqib")->"t.registers.ff[6]._sqi"+ "t.registers.ff[6]._sqib"->"t.registers.ff[6].q"- ~("t.registers.ff[6]._sqib")->"t.registers.ff[6].q"+ -"t.registers.ff[7].clk"->"t.registers.ff[7]._clk"- -~("t.registers.ff[7].clk")->"t.registers.ff[7]._clk"+ -"t.registers.ff[7]._clk"->"t.registers.ff[7].__clk"- -~("t.registers.ff[7]._clk")->"t.registers.ff[7].__clk"+ -~"t.registers.ff[7].d"&~"t.registers.ff[7]._clk"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7].__clk"&~"t.registers.ff[7]._mqi"->"t.registers.ff[7]._mqib"+ -"t.registers.ff[7].d"&"t.registers.ff[7].__clk"|"t.registers.ff[7].reset_B"&"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk"->"t.registers.ff[7]._mqib"- +"t.registers.ff[7].clk_B"->"t.registers.ff[7]._clk_B"- +~("t.registers.ff[7].clk_B")->"t.registers.ff[7]._clk_B"+ +"t.registers.ff[7]._clk_B"->"t.registers.ff[7].__clk_B"- +~("t.registers.ff[7]._clk_B")->"t.registers.ff[7].__clk_B"+ +~"t.registers.ff[7].d"&~"t.registers.ff[7]._clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7].__clk_B"&~"t.registers.ff[7]._mqi"->"t.registers.ff[7]._mqib"+ +("t.registers.ff[7].d"&"t.registers.ff[7].__clk_B"|"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._mqib"- "t.registers.ff[7]._mqib"->"t.registers.ff[7]._mqi"- ~("t.registers.ff[7]._mqib")->"t.registers.ff[7]._mqi"+ -~"t.registers.ff[7]._mqi"&~"t.registers.ff[7].__clk"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7]._sqi"&~"t.registers.ff[7]._clk"->"t.registers.ff[7]._sqib"+ -"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk"|"t.registers.ff[7]._sqi"&"t.registers.ff[7].__clk"&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._sqib"- +~"t.registers.ff[7]._mqi"&~"t.registers.ff[7].__clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7]._sqi"&~"t.registers.ff[7]._clk_B"->"t.registers.ff[7]._sqib"+ +("t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B"|"t.registers.ff[7]._sqi"&"t.registers.ff[7].__clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._sqib"- "t.registers.ff[7]._sqib"->"t.registers.ff[7]._sqi"- ~("t.registers.ff[7]._sqib")->"t.registers.ff[7]._sqi"+ "t.registers.ff[7]._sqib"->"t.registers.ff[7].q"- ~("t.registers.ff[7]._sqib")->"t.registers.ff[7].q"+ -"t.registers.ff[8].clk"->"t.registers.ff[8]._clk"- -~("t.registers.ff[8].clk")->"t.registers.ff[8]._clk"+ -"t.registers.ff[8]._clk"->"t.registers.ff[8].__clk"- -~("t.registers.ff[8]._clk")->"t.registers.ff[8].__clk"+ -~"t.registers.ff[8].d"&~"t.registers.ff[8]._clk"|~"t.registers.ff[8].reset_B"|~"t.registers.ff[8].__clk"&~"t.registers.ff[8]._mqi"->"t.registers.ff[8]._mqib"+ -"t.registers.ff[8].d"&"t.registers.ff[8].__clk"|"t.registers.ff[8].reset_B"&"t.registers.ff[8]._mqi"&"t.registers.ff[8]._clk"->"t.registers.ff[8]._mqib"- -"t.registers.ff[8]._mqib"->"t.registers.ff[8]._mqi"- -~("t.registers.ff[8]._mqib")->"t.registers.ff[8]._mqi"+ -~"t.registers.ff[8]._mqi"&~"t.registers.ff[8].__clk"|~"t.registers.ff[8].reset_B"|~"t.registers.ff[8]._sqi"&~"t.registers.ff[8]._clk"->"t.registers.ff[8]._sqib"+ -"t.registers.ff[8]._mqi"&"t.registers.ff[8]._clk"|"t.registers.ff[8]._sqi"&"t.registers.ff[8].__clk"&"t.registers.ff[8].reset_B"->"t.registers.ff[8]._sqib"- -"t.registers.ff[8]._sqib"->"t.registers.ff[8]._sqi"- -~("t.registers.ff[8]._sqib")->"t.registers.ff[8]._sqi"+ -"t.registers.ff[8]._sqib"->"t.registers.ff[8].q"- -~("t.registers.ff[8]._sqib")->"t.registers.ff[8].q"+ -"t.registers.ff[9].clk"->"t.registers.ff[9]._clk"- -~("t.registers.ff[9].clk")->"t.registers.ff[9]._clk"+ -"t.registers.ff[9]._clk"->"t.registers.ff[9].__clk"- -~("t.registers.ff[9]._clk")->"t.registers.ff[9].__clk"+ -~"t.registers.ff[9].d"&~"t.registers.ff[9]._clk"|~"t.registers.ff[9].reset_B"|~"t.registers.ff[9].__clk"&~"t.registers.ff[9]._mqi"->"t.registers.ff[9]._mqib"+ -"t.registers.ff[9].d"&"t.registers.ff[9].__clk"|"t.registers.ff[9].reset_B"&"t.registers.ff[9]._mqi"&"t.registers.ff[9]._clk"->"t.registers.ff[9]._mqib"- -"t.registers.ff[9]._mqib"->"t.registers.ff[9]._mqi"- -~("t.registers.ff[9]._mqib")->"t.registers.ff[9]._mqi"+ -~"t.registers.ff[9]._mqi"&~"t.registers.ff[9].__clk"|~"t.registers.ff[9].reset_B"|~"t.registers.ff[9]._sqi"&~"t.registers.ff[9]._clk"->"t.registers.ff[9]._sqib"+ -"t.registers.ff[9]._mqi"&"t.registers.ff[9]._clk"|"t.registers.ff[9]._sqi"&"t.registers.ff[9].__clk"&"t.registers.ff[9].reset_B"->"t.registers.ff[9]._sqib"- -"t.registers.ff[9]._sqib"->"t.registers.ff[9]._sqi"- -~("t.registers.ff[9]._sqib")->"t.registers.ff[9]._sqi"+ -"t.registers.ff[9]._sqib"->"t.registers.ff[9].q"- -~("t.registers.ff[9]._sqib")->"t.registers.ff[9].q"+ -"t.registers.ff[10].clk"->"t.registers.ff[10]._clk"- -~("t.registers.ff[10].clk")->"t.registers.ff[10]._clk"+ -"t.registers.ff[10]._clk"->"t.registers.ff[10].__clk"- -~("t.registers.ff[10]._clk")->"t.registers.ff[10].__clk"+ -~"t.registers.ff[10].d"&~"t.registers.ff[10]._clk"|~"t.registers.ff[10].reset_B"|~"t.registers.ff[10].__clk"&~"t.registers.ff[10]._mqi"->"t.registers.ff[10]._mqib"+ -"t.registers.ff[10].d"&"t.registers.ff[10].__clk"|"t.registers.ff[10].reset_B"&"t.registers.ff[10]._mqi"&"t.registers.ff[10]._clk"->"t.registers.ff[10]._mqib"- -"t.registers.ff[10]._mqib"->"t.registers.ff[10]._mqi"- -~("t.registers.ff[10]._mqib")->"t.registers.ff[10]._mqi"+ -~"t.registers.ff[10]._mqi"&~"t.registers.ff[10].__clk"|~"t.registers.ff[10].reset_B"|~"t.registers.ff[10]._sqi"&~"t.registers.ff[10]._clk"->"t.registers.ff[10]._sqib"+ -"t.registers.ff[10]._mqi"&"t.registers.ff[10]._clk"|"t.registers.ff[10]._sqi"&"t.registers.ff[10].__clk"&"t.registers.ff[10].reset_B"->"t.registers.ff[10]._sqib"- -"t.registers.ff[10]._sqib"->"t.registers.ff[10]._sqi"- -~("t.registers.ff[10]._sqib")->"t.registers.ff[10]._sqi"+ -"t.registers.ff[10]._sqib"->"t.registers.ff[10].q"- -~("t.registers.ff[10]._sqib")->"t.registers.ff[10].q"+ -"t.registers.ff[11].clk"->"t.registers.ff[11]._clk"- -~("t.registers.ff[11].clk")->"t.registers.ff[11]._clk"+ -"t.registers.ff[11]._clk"->"t.registers.ff[11].__clk"- -~("t.registers.ff[11]._clk")->"t.registers.ff[11].__clk"+ -~"t.registers.ff[11].d"&~"t.registers.ff[11]._clk"|~"t.registers.ff[11].reset_B"|~"t.registers.ff[11].__clk"&~"t.registers.ff[11]._mqi"->"t.registers.ff[11]._mqib"+ -"t.registers.ff[11].d"&"t.registers.ff[11].__clk"|"t.registers.ff[11].reset_B"&"t.registers.ff[11]._mqi"&"t.registers.ff[11]._clk"->"t.registers.ff[11]._mqib"- -"t.registers.ff[11]._mqib"->"t.registers.ff[11]._mqi"- -~("t.registers.ff[11]._mqib")->"t.registers.ff[11]._mqi"+ -~"t.registers.ff[11]._mqi"&~"t.registers.ff[11].__clk"|~"t.registers.ff[11].reset_B"|~"t.registers.ff[11]._sqi"&~"t.registers.ff[11]._clk"->"t.registers.ff[11]._sqib"+ -"t.registers.ff[11]._mqi"&"t.registers.ff[11]._clk"|"t.registers.ff[11]._sqi"&"t.registers.ff[11].__clk"&"t.registers.ff[11].reset_B"->"t.registers.ff[11]._sqib"- -"t.registers.ff[11]._sqib"->"t.registers.ff[11]._sqi"- -~("t.registers.ff[11]._sqib")->"t.registers.ff[11]._sqi"+ -"t.registers.ff[11]._sqib"->"t.registers.ff[11].q"- -~("t.registers.ff[11]._sqib")->"t.registers.ff[11].q"+ -"t.registers.ff[12].clk"->"t.registers.ff[12]._clk"- -~("t.registers.ff[12].clk")->"t.registers.ff[12]._clk"+ -"t.registers.ff[12]._clk"->"t.registers.ff[12].__clk"- -~("t.registers.ff[12]._clk")->"t.registers.ff[12].__clk"+ -~"t.registers.ff[12].d"&~"t.registers.ff[12]._clk"|~"t.registers.ff[12].reset_B"|~"t.registers.ff[12].__clk"&~"t.registers.ff[12]._mqi"->"t.registers.ff[12]._mqib"+ -"t.registers.ff[12].d"&"t.registers.ff[12].__clk"|"t.registers.ff[12].reset_B"&"t.registers.ff[12]._mqi"&"t.registers.ff[12]._clk"->"t.registers.ff[12]._mqib"- -"t.registers.ff[12]._mqib"->"t.registers.ff[12]._mqi"- -~("t.registers.ff[12]._mqib")->"t.registers.ff[12]._mqi"+ -~"t.registers.ff[12]._mqi"&~"t.registers.ff[12].__clk"|~"t.registers.ff[12].reset_B"|~"t.registers.ff[12]._sqi"&~"t.registers.ff[12]._clk"->"t.registers.ff[12]._sqib"+ -"t.registers.ff[12]._mqi"&"t.registers.ff[12]._clk"|"t.registers.ff[12]._sqi"&"t.registers.ff[12].__clk"&"t.registers.ff[12].reset_B"->"t.registers.ff[12]._sqib"- -"t.registers.ff[12]._sqib"->"t.registers.ff[12]._sqi"- -~("t.registers.ff[12]._sqib")->"t.registers.ff[12]._sqi"+ -"t.registers.ff[12]._sqib"->"t.registers.ff[12].q"- -~("t.registers.ff[12]._sqib")->"t.registers.ff[12].q"+ -"t.registers.ff[13].clk"->"t.registers.ff[13]._clk"- -~("t.registers.ff[13].clk")->"t.registers.ff[13]._clk"+ -"t.registers.ff[13]._clk"->"t.registers.ff[13].__clk"- -~("t.registers.ff[13]._clk")->"t.registers.ff[13].__clk"+ -~"t.registers.ff[13].d"&~"t.registers.ff[13]._clk"|~"t.registers.ff[13].reset_B"|~"t.registers.ff[13].__clk"&~"t.registers.ff[13]._mqi"->"t.registers.ff[13]._mqib"+ -"t.registers.ff[13].d"&"t.registers.ff[13].__clk"|"t.registers.ff[13].reset_B"&"t.registers.ff[13]._mqi"&"t.registers.ff[13]._clk"->"t.registers.ff[13]._mqib"- -"t.registers.ff[13]._mqib"->"t.registers.ff[13]._mqi"- -~("t.registers.ff[13]._mqib")->"t.registers.ff[13]._mqi"+ -~"t.registers.ff[13]._mqi"&~"t.registers.ff[13].__clk"|~"t.registers.ff[13].reset_B"|~"t.registers.ff[13]._sqi"&~"t.registers.ff[13]._clk"->"t.registers.ff[13]._sqib"+ -"t.registers.ff[13]._mqi"&"t.registers.ff[13]._clk"|"t.registers.ff[13]._sqi"&"t.registers.ff[13].__clk"&"t.registers.ff[13].reset_B"->"t.registers.ff[13]._sqib"- -"t.registers.ff[13]._sqib"->"t.registers.ff[13]._sqi"- -~("t.registers.ff[13]._sqib")->"t.registers.ff[13]._sqi"+ -"t.registers.ff[13]._sqib"->"t.registers.ff[13].q"- -~("t.registers.ff[13]._sqib")->"t.registers.ff[13].q"+ -"t.registers.ff[14].clk"->"t.registers.ff[14]._clk"- -~("t.registers.ff[14].clk")->"t.registers.ff[14]._clk"+ -"t.registers.ff[14]._clk"->"t.registers.ff[14].__clk"- -~("t.registers.ff[14]._clk")->"t.registers.ff[14].__clk"+ -~"t.registers.ff[14].d"&~"t.registers.ff[14]._clk"|~"t.registers.ff[14].reset_B"|~"t.registers.ff[14].__clk"&~"t.registers.ff[14]._mqi"->"t.registers.ff[14]._mqib"+ -"t.registers.ff[14].d"&"t.registers.ff[14].__clk"|"t.registers.ff[14].reset_B"&"t.registers.ff[14]._mqi"&"t.registers.ff[14]._clk"->"t.registers.ff[14]._mqib"- -"t.registers.ff[14]._mqib"->"t.registers.ff[14]._mqi"- -~("t.registers.ff[14]._mqib")->"t.registers.ff[14]._mqi"+ -~"t.registers.ff[14]._mqi"&~"t.registers.ff[14].__clk"|~"t.registers.ff[14].reset_B"|~"t.registers.ff[14]._sqi"&~"t.registers.ff[14]._clk"->"t.registers.ff[14]._sqib"+ -"t.registers.ff[14]._mqi"&"t.registers.ff[14]._clk"|"t.registers.ff[14]._sqi"&"t.registers.ff[14].__clk"&"t.registers.ff[14].reset_B"->"t.registers.ff[14]._sqib"- -"t.registers.ff[14]._sqib"->"t.registers.ff[14]._sqi"- -~("t.registers.ff[14]._sqib")->"t.registers.ff[14]._sqi"+ -"t.registers.ff[14]._sqib"->"t.registers.ff[14].q"- -~("t.registers.ff[14]._sqib")->"t.registers.ff[14].q"+ -"t.registers.ff[15].clk"->"t.registers.ff[15]._clk"- -~("t.registers.ff[15].clk")->"t.registers.ff[15]._clk"+ -"t.registers.ff[15]._clk"->"t.registers.ff[15].__clk"- -~("t.registers.ff[15]._clk")->"t.registers.ff[15].__clk"+ -~"t.registers.ff[15].d"&~"t.registers.ff[15]._clk"|~"t.registers.ff[15].reset_B"|~"t.registers.ff[15].__clk"&~"t.registers.ff[15]._mqi"->"t.registers.ff[15]._mqib"+ -"t.registers.ff[15].d"&"t.registers.ff[15].__clk"|"t.registers.ff[15].reset_B"&"t.registers.ff[15]._mqi"&"t.registers.ff[15]._clk"->"t.registers.ff[15]._mqib"- -"t.registers.ff[15]._mqib"->"t.registers.ff[15]._mqi"- -~("t.registers.ff[15]._mqib")->"t.registers.ff[15]._mqi"+ -~"t.registers.ff[15]._mqi"&~"t.registers.ff[15].__clk"|~"t.registers.ff[15].reset_B"|~"t.registers.ff[15]._sqi"&~"t.registers.ff[15]._clk"->"t.registers.ff[15]._sqib"+ -"t.registers.ff[15]._mqi"&"t.registers.ff[15]._clk"|"t.registers.ff[15]._sqi"&"t.registers.ff[15].__clk"&"t.registers.ff[15].reset_B"->"t.registers.ff[15]._sqib"- -"t.registers.ff[15]._sqib"->"t.registers.ff[15]._sqi"- -~("t.registers.ff[15]._sqib")->"t.registers.ff[15]._sqi"+ -"t.registers.ff[15]._sqib"->"t.registers.ff[15].q"- -~("t.registers.ff[15]._sqib")->"t.registers.ff[15].q"+ += "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[1]" += "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[0]" += "t.registers.ff[7].clk_B" "t.registers.ff[6].clk_B" += "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[1]" += "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[0]" += "t.registers.ff[5].clk_B" "t.registers.ff[4].clk_B" += "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[1]" += "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[0]" += "t.registers.ff[3].clk_B" "t.registers.ff[2].clk_B" += "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[1]" += "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[0]" += "t.registers.ff[1].clk_B" "t.registers.ff[0].clk_B" += "t.registers._clock_temp_inv" "t.registers.clk_X.in" += "t.registers._clock_temp_inv" "t.registers.inv_clk.y" = "t.registers.reset_mem_B" "t.registers.reset_buf_BXX.a" "t.registers.clk_X.buf1.a"->"t.registers.clk_X.buf1._y"- ~("t.registers.clk_X.buf1.a")->"t.registers.clk_X.buf1._y"+ @@ -337,29 +223,29 @@ = "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]" = "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f" = "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t" -= "t.registers.in.d.d[3].d[0]" "t.registers.atree[5].in[1]" -= "t.registers.in.d.d[3].d[0]" "t.registers.atree[4].in[1]" = "t.registers.in.d.d[3].d[0]" "t.registers.atree[1].in[1]" = "t.registers.in.d.d[3].d[0]" "t.registers.atree[0].in[1]" = "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f" -= "t.registers.in.d.d[3].d[1]" "t.registers.atree[7].in[1]" -= "t.registers.in.d.d[3].d[1]" "t.registers.atree[6].in[1]" = "t.registers.in.d.d[3].d[1]" "t.registers.atree[3].in[1]" = "t.registers.in.d.d[3].d[1]" "t.registers.atree[2].in[1]" = "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t" -= "t.registers.in.d.d[2].d[0]" "t.registers.atree[6].in[0]" -= "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[0]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[2].in[0]" = "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[0]" = "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f" -= "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[0]" -= "t.registers.in.d.d[2].d[1]" "t.registers.atree[5].in[0]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[0]" = "t.registers.in.d.d[2].d[1]" "t.registers.atree[1].in[0]" = "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t" = "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f" += "t.registers.in.d.d[1].d[1]" "t.registers.ff[7].d" += "t.registers.in.d.d[1].d[1]" "t.registers.ff[5].d" += "t.registers.in.d.d[1].d[1]" "t.registers.ff[3].d" += "t.registers.in.d.d[1].d[1]" "t.registers.ff[1].d" = "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t" = "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f" += "t.registers.in.d.d[0].d[1]" "t.registers.ff[6].d" += "t.registers.in.d.d[0].d[1]" "t.registers.ff[4].d" += "t.registers.in.d.d[0].d[1]" "t.registers.ff[2].d" += "t.registers.in.d.d[0].d[1]" "t.registers.ff[0].d" = "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t" "t.registers.reset_buf_BX.a"->"t.registers.reset_buf_BX._y"- ~("t.registers.reset_buf_BX.a")->"t.registers.reset_buf_BX._y"+ @@ -450,22 +336,14 @@ = "t.registers._reset_mem_BXX[5]" "t.registers.reset_bufarray.out[5]" = "t.registers._reset_mem_BXX[6]" "t.registers.reset_bufarray.out[6]" = "t.registers._reset_mem_BXX[7]" "t.registers.reset_bufarray.out[7]" -= "t.registers._reset_mem_BXX[8]" "t.registers.reset_bufarray.out[8]" -= "t.registers._reset_mem_BXX[9]" "t.registers.reset_bufarray.out[9]" -= "t.registers._reset_mem_BXX[10]" "t.registers.reset_bufarray.out[10]" -= "t.registers._reset_mem_BXX[11]" "t.registers.reset_bufarray.out[11]" -= "t.registers._reset_mem_BXX[12]" "t.registers.reset_bufarray.out[12]" -= "t.registers._reset_mem_BXX[13]" "t.registers.reset_bufarray.out[13]" -= "t.registers._reset_mem_BXX[14]" "t.registers.reset_bufarray.out[14]" -= "t.registers._reset_mem_BXX[15]" "t.registers.reset_bufarray.out[15]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[15]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[14]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[13]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[12]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[11]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[10]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[9]" -= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[8]" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[7].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[6].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[5].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[4].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[3].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[2].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[1].reset_B" += "t.registers._reset_mem_BXX[0]" "t.registers.ff[0].reset_B" = "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[7]" = "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[6]" = "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[5]" @@ -481,14 +359,6 @@ = "t.registers._out_encoder[2]" "t.registers.atree[2].out" = "t.registers._out_encoder[3]" "t.registers.and_encoder[3].a" = "t.registers._out_encoder[3]" "t.registers.atree[3].out" -= "t.registers._out_encoder[4]" "t.registers.and_encoder[4].a" -= "t.registers._out_encoder[4]" "t.registers.atree[4].out" -= "t.registers._out_encoder[5]" "t.registers.and_encoder[5].a" -= "t.registers._out_encoder[5]" "t.registers.atree[5].out" -= "t.registers._out_encoder[6]" "t.registers.and_encoder[6].a" -= "t.registers._out_encoder[6]" "t.registers.atree[6].out" -= "t.registers._out_encoder[7]" "t.registers.and_encoder[7].a" -= "t.registers._out_encoder[7]" "t.registers.atree[7].out" = "t.registers._clock_word_temp[0]" "t.registers.clock_buffer[0].in" = "t.registers._clock_word_temp[0]" "t.registers.and_encoder[0].y" = "t.registers._clock_word_temp[1]" "t.registers.clock_buffer[1].in" @@ -497,14 +367,22 @@ = "t.registers._clock_word_temp[2]" "t.registers.and_encoder[2].y" = "t.registers._clock_word_temp[3]" "t.registers.clock_buffer[3].in" = "t.registers._clock_word_temp[3]" "t.registers.and_encoder[3].y" -= "t.registers._clock_word_temp[4]" "t.registers.clock_buffer[4].in" -= "t.registers._clock_word_temp[4]" "t.registers.and_encoder[4].y" -= "t.registers._clock_word_temp[5]" "t.registers.clock_buffer[5].in" -= "t.registers._clock_word_temp[5]" "t.registers.and_encoder[5].y" -= "t.registers._clock_word_temp[6]" "t.registers.clock_buffer[6].in" -= "t.registers._clock_word_temp[6]" "t.registers.and_encoder[6].y" -= "t.registers._clock_word_temp[7]" "t.registers.clock_buffer[7].in" -= "t.registers._clock_word_temp[7]" "t.registers.and_encoder[7].y" +"t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b"->"t.registers.and_encoder[0]._y"- +~("t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b")->"t.registers.and_encoder[0]._y"+ +"t.registers.and_encoder[0]._y"->"t.registers.and_encoder[0].y"- +~("t.registers.and_encoder[0]._y")->"t.registers.and_encoder[0].y"+ +"t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b"->"t.registers.and_encoder[1]._y"- +~("t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b")->"t.registers.and_encoder[1]._y"+ +"t.registers.and_encoder[1]._y"->"t.registers.and_encoder[1].y"- +~("t.registers.and_encoder[1]._y")->"t.registers.and_encoder[1].y"+ +"t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b"->"t.registers.and_encoder[2]._y"- +~("t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b")->"t.registers.and_encoder[2]._y"+ +"t.registers.and_encoder[2]._y"->"t.registers.and_encoder[2].y"- +~("t.registers.and_encoder[2]._y")->"t.registers.and_encoder[2].y"+ +"t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b"->"t.registers.and_encoder[3]._y"- +~("t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b")->"t.registers.and_encoder[3]._y"+ +"t.registers.and_encoder[3]._y"->"t.registers.and_encoder[3].y"- +~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+ = "t.registers._in_temp.d[0].d[0]" "t.registers._in_temp.d[0].f" = "t.registers._in_temp.d[0].d[1]" "t.registers._in_temp.d[0].t" = "t.registers._in_temp.d[1].d[0]" "t.registers._in_temp.d[1].f" @@ -547,48 +425,8 @@ = "t.registers._in_temp.d[4].d[1]" "t.registers.val_input.in.d[4].d[1]" = "t.registers._reset_mem_BX" "t.registers.reset_bufarray.in" = "t.registers._reset_mem_BX" "t.registers.reset_buf_BXX.y" -"t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b"->"t.registers.and_encoder[0]._y"- -~("t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b")->"t.registers.and_encoder[0]._y"+ -"t.registers.and_encoder[0]._y"->"t.registers.and_encoder[0].y"- -~("t.registers.and_encoder[0]._y")->"t.registers.and_encoder[0].y"+ -"t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b"->"t.registers.and_encoder[1]._y"- -~("t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b")->"t.registers.and_encoder[1]._y"+ -"t.registers.and_encoder[1]._y"->"t.registers.and_encoder[1].y"- -~("t.registers.and_encoder[1]._y")->"t.registers.and_encoder[1].y"+ -"t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b"->"t.registers.and_encoder[2]._y"- -~("t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b")->"t.registers.and_encoder[2]._y"+ -"t.registers.and_encoder[2]._y"->"t.registers.and_encoder[2].y"- -~("t.registers.and_encoder[2]._y")->"t.registers.and_encoder[2].y"+ -"t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b"->"t.registers.and_encoder[3]._y"- -~("t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b")->"t.registers.and_encoder[3]._y"+ -"t.registers.and_encoder[3]._y"->"t.registers.and_encoder[3].y"- -~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+ -"t.registers.and_encoder[4].a"&"t.registers.and_encoder[4].b"->"t.registers.and_encoder[4]._y"- -~("t.registers.and_encoder[4].a"&"t.registers.and_encoder[4].b")->"t.registers.and_encoder[4]._y"+ -"t.registers.and_encoder[4]._y"->"t.registers.and_encoder[4].y"- -~("t.registers.and_encoder[4]._y")->"t.registers.and_encoder[4].y"+ -"t.registers.and_encoder[5].a"&"t.registers.and_encoder[5].b"->"t.registers.and_encoder[5]._y"- -~("t.registers.and_encoder[5].a"&"t.registers.and_encoder[5].b")->"t.registers.and_encoder[5]._y"+ -"t.registers.and_encoder[5]._y"->"t.registers.and_encoder[5].y"- -~("t.registers.and_encoder[5]._y")->"t.registers.and_encoder[5].y"+ -"t.registers.and_encoder[6].a"&"t.registers.and_encoder[6].b"->"t.registers.and_encoder[6]._y"- -~("t.registers.and_encoder[6].a"&"t.registers.and_encoder[6].b")->"t.registers.and_encoder[6]._y"+ -"t.registers.and_encoder[6]._y"->"t.registers.and_encoder[6].y"- -~("t.registers.and_encoder[6]._y")->"t.registers.and_encoder[6].y"+ -"t.registers.and_encoder[7].a"&"t.registers.and_encoder[7].b"->"t.registers.and_encoder[7]._y"- -~("t.registers.and_encoder[7].a"&"t.registers.and_encoder[7].b")->"t.registers.and_encoder[7]._y"+ -"t.registers.and_encoder[7]._y"->"t.registers.and_encoder[7].y"- -~("t.registers.and_encoder[7]._y")->"t.registers.and_encoder[7].y"+ = "t.registers._in_a_temp" "t.registers.ack_input_X.in" = "t.registers._in_a_temp" "t.registers.ack_dly.out" -= "t.registers.supply.vss" "t.registers.clock_buffer[7].supply.vss" -= "t.registers.supply.vdd" "t.registers.clock_buffer[7].supply.vdd" -= "t.registers.supply.vss" "t.registers.clock_buffer[6].supply.vss" -= "t.registers.supply.vdd" "t.registers.clock_buffer[6].supply.vdd" -= "t.registers.supply.vss" "t.registers.clock_buffer[5].supply.vss" -= "t.registers.supply.vdd" "t.registers.clock_buffer[5].supply.vdd" -= "t.registers.supply.vss" "t.registers.clock_buffer[4].supply.vss" -= "t.registers.supply.vdd" "t.registers.clock_buffer[4].supply.vdd" = "t.registers.supply.vss" "t.registers.clock_buffer[3].supply.vss" = "t.registers.supply.vdd" "t.registers.clock_buffer[3].supply.vdd" = "t.registers.supply.vss" "t.registers.clock_buffer[2].supply.vss" @@ -597,14 +435,6 @@ = "t.registers.supply.vdd" "t.registers.clock_buffer[1].supply.vdd" = "t.registers.supply.vss" "t.registers.clock_buffer[0].supply.vss" = "t.registers.supply.vdd" "t.registers.clock_buffer[0].supply.vdd" -= "t.registers.supply.vss" "t.registers.atree[7].supply.vss" -= "t.registers.supply.vdd" "t.registers.atree[7].supply.vdd" -= "t.registers.supply.vss" "t.registers.atree[6].supply.vss" -= "t.registers.supply.vdd" "t.registers.atree[6].supply.vdd" -= "t.registers.supply.vss" "t.registers.atree[5].supply.vss" -= "t.registers.supply.vdd" "t.registers.atree[5].supply.vdd" -= "t.registers.supply.vss" "t.registers.atree[4].supply.vss" -= "t.registers.supply.vdd" "t.registers.atree[4].supply.vdd" = "t.registers.supply.vss" "t.registers.atree[3].supply.vss" = "t.registers.supply.vdd" "t.registers.atree[3].supply.vdd" = "t.registers.supply.vss" "t.registers.atree[2].supply.vss" @@ -627,30 +457,50 @@ = "t.registers.supply.vdd" "t.registers.val_input_X.supply.vdd" = "t.registers.supply.vss" "t.registers.val_input.supply.vss" = "t.registers.supply.vdd" "t.registers.val_input.supply.vdd" -= "t.registers.supply.vdd" "t.registers.and_encoder[7].vdd" -= "t.registers.supply.vdd" "t.registers.and_encoder[6].vdd" -= "t.registers.supply.vdd" "t.registers.and_encoder[5].vdd" -= "t.registers.supply.vdd" "t.registers.and_encoder[4].vdd" += "t.registers.supply.vdd" "t.registers.ff[7].vdd" += "t.registers.supply.vdd" "t.registers.ff[6].vdd" = "t.registers.supply.vdd" "t.registers.and_encoder[3].vdd" += "t.registers.supply.vdd" "t.registers.ff[5].vdd" += "t.registers.supply.vdd" "t.registers.ff[4].vdd" = "t.registers.supply.vdd" "t.registers.and_encoder[2].vdd" += "t.registers.supply.vdd" "t.registers.ff[3].vdd" += "t.registers.supply.vdd" "t.registers.ff[2].vdd" = "t.registers.supply.vdd" "t.registers.and_encoder[1].vdd" += "t.registers.supply.vdd" "t.registers.ff[1].vdd" += "t.registers.supply.vdd" "t.registers.ff[0].vdd" = "t.registers.supply.vdd" "t.registers.and_encoder[0].vdd" = "t.registers.supply.vdd" "t.registers.reset_buf_BXX.vdd" = "t.registers.supply.vdd" "t.registers.reset_buf_BX.vdd" -= "t.registers.supply.vss" "t.registers.and_encoder[7].vss" -= "t.registers.supply.vss" "t.registers.and_encoder[6].vss" -= "t.registers.supply.vss" "t.registers.and_encoder[5].vss" -= "t.registers.supply.vss" "t.registers.and_encoder[4].vss" += "t.registers.supply.vdd" "t.registers.inv_clk.vdd" += "t.registers.supply.vss" "t.registers.ff[7].vss" += "t.registers.supply.vss" "t.registers.ff[6].vss" = "t.registers.supply.vss" "t.registers.and_encoder[3].vss" += "t.registers.supply.vss" "t.registers.ff[5].vss" += "t.registers.supply.vss" "t.registers.ff[4].vss" = "t.registers.supply.vss" "t.registers.and_encoder[2].vss" += "t.registers.supply.vss" "t.registers.ff[3].vss" += "t.registers.supply.vss" "t.registers.ff[2].vss" = "t.registers.supply.vss" "t.registers.and_encoder[1].vss" += "t.registers.supply.vss" "t.registers.ff[1].vss" += "t.registers.supply.vss" "t.registers.ff[0].vss" = "t.registers.supply.vss" "t.registers.and_encoder[0].vss" = "t.registers.supply.vss" "t.registers.reset_buf_BXX.vss" = "t.registers.supply.vss" "t.registers.reset_buf_BX.vss" += "t.registers.supply.vss" "t.registers.inv_clk.vss" = "t.registers.dly_cfg[0]" "t.registers.ack_dly.s[0]" = "t.registers.dly_cfg[1]" "t.registers.ack_dly.s[1]" = "t.registers.dly_cfg[0]" "t.registers.clk_dly.s[0]" = "t.registers.dly_cfg[1]" "t.registers.clk_dly.s[1]" +"t.registers.inv_clk.a"->"t.registers.inv_clk.y"- +~("t.registers.inv_clk.a")->"t.registers.inv_clk.y"+ += "t.registers.data[3].d[0]" "t.registers.ff[6].q" += "t.registers.data[3].d[1]" "t.registers.ff[7].q" += "t.registers.data[2].d[0]" "t.registers.ff[4].q" += "t.registers.data[2].d[1]" "t.registers.ff[5].q" += "t.registers.data[1].d[0]" "t.registers.ff[2].q" += "t.registers.data[1].d[1]" "t.registers.ff[3].q" += "t.registers.data[0].d[0]" "t.registers.ff[0].q" += "t.registers.data[0].d[1]" "t.registers.ff[1].q" "t.registers.val_input_X.buf1.a"->"t.registers.val_input_X.buf1._y"- ~("t.registers.val_input_X.buf1.a")->"t.registers.val_input_X.buf1._y"+ "t.registers.val_input_X.buf1._y"->"t.registers.val_input_X.buf1.y"- @@ -667,30 +517,54 @@ = "t.registers.ack_input_X.supply.vss" "t.registers.ack_input_X.buf1.vss" = "t.registers.ack_input_X.out" "t.registers.ack_input_X.buf1.y" = "t.registers.ack_input_X.in" "t.registers.ack_input_X.buf1.a" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[8]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[7]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[6]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[5]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[4]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[3]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[2]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[0]" -= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[1]" -= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[0]" += "t.registers.atree[0].supply.vdd" "t.registers.atree[0].and2s[0].vdd" += "t.registers.atree[0].supply.vss" "t.registers.atree[0].and2s[0].vss" +"t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b"->"t.registers.atree[0].and2s[0]._y"- +~("t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b")->"t.registers.atree[0].and2s[0]._y"+ +"t.registers.atree[0].and2s[0]._y"->"t.registers.atree[0].and2s[0].y"- +~("t.registers.atree[0].and2s[0]._y")->"t.registers.atree[0].and2s[0].y"+ += "t.registers.atree[0].in[0]" "t.registers.atree[0].and2s[0].a" += "t.registers.atree[0].in[0]" "t.registers.atree[0].tmp[0]" += "t.registers.atree[0].in[1]" "t.registers.atree[0].and2s[0].b" += "t.registers.atree[0].in[1]" "t.registers.atree[0].tmp[1]" += "t.registers.atree[0].out" "t.registers.atree[0].and2s[0].y" += "t.registers.atree[0].out" "t.registers.atree[0].tmp[2]" += "t.registers.atree[1].supply.vdd" "t.registers.atree[1].and2s[0].vdd" += "t.registers.atree[1].supply.vss" "t.registers.atree[1].and2s[0].vss" +"t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b"->"t.registers.atree[1].and2s[0]._y"- +~("t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b")->"t.registers.atree[1].and2s[0]._y"+ +"t.registers.atree[1].and2s[0]._y"->"t.registers.atree[1].and2s[0].y"- +~("t.registers.atree[1].and2s[0]._y")->"t.registers.atree[1].and2s[0].y"+ += "t.registers.atree[1].in[0]" "t.registers.atree[1].and2s[0].a" += "t.registers.atree[1].in[0]" "t.registers.atree[1].tmp[0]" += "t.registers.atree[1].in[1]" "t.registers.atree[1].and2s[0].b" += "t.registers.atree[1].in[1]" "t.registers.atree[1].tmp[1]" += "t.registers.atree[1].out" "t.registers.atree[1].and2s[0].y" += "t.registers.atree[1].out" "t.registers.atree[1].tmp[2]" += "t.registers.atree[2].supply.vdd" "t.registers.atree[2].and2s[0].vdd" += "t.registers.atree[2].supply.vss" "t.registers.atree[2].and2s[0].vss" +"t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b"->"t.registers.atree[2].and2s[0]._y"- +~("t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b")->"t.registers.atree[2].and2s[0]._y"+ +"t.registers.atree[2].and2s[0]._y"->"t.registers.atree[2].and2s[0].y"- +~("t.registers.atree[2].and2s[0]._y")->"t.registers.atree[2].and2s[0].y"+ += "t.registers.atree[2].in[0]" "t.registers.atree[2].and2s[0].a" += "t.registers.atree[2].in[0]" "t.registers.atree[2].tmp[0]" += "t.registers.atree[2].in[1]" "t.registers.atree[2].and2s[0].b" += "t.registers.atree[2].in[1]" "t.registers.atree[2].tmp[1]" += "t.registers.atree[2].out" "t.registers.atree[2].and2s[0].y" += "t.registers.atree[2].out" "t.registers.atree[2].tmp[2]" += "t.registers.atree[3].supply.vdd" "t.registers.atree[3].and2s[0].vdd" += "t.registers.atree[3].supply.vss" "t.registers.atree[3].and2s[0].vss" +"t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b"->"t.registers.atree[3].and2s[0]._y"- +~("t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b")->"t.registers.atree[3].and2s[0]._y"+ +"t.registers.atree[3].and2s[0]._y"->"t.registers.atree[3].and2s[0].y"- +~("t.registers.atree[3].and2s[0]._y")->"t.registers.atree[3].and2s[0].y"+ += "t.registers.atree[3].in[0]" "t.registers.atree[3].and2s[0].a" += "t.registers.atree[3].in[0]" "t.registers.atree[3].tmp[0]" += "t.registers.atree[3].in[1]" "t.registers.atree[3].and2s[0].b" += "t.registers.atree[3].in[1]" "t.registers.atree[3].tmp[1]" += "t.registers.atree[3].out" "t.registers.atree[3].and2s[0].y" += "t.registers.atree[3].out" "t.registers.atree[3].tmp[2]" ~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+ "t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"- "t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"- @@ -882,102 +756,6 @@ ~("t.registers.reset_buf_BXX.a")->"t.registers.reset_buf_BXX._y"+ "t.registers.reset_buf_BXX._y"->"t.registers.reset_buf_BXX.y"- ~("t.registers.reset_buf_BXX._y")->"t.registers.reset_buf_BXX.y"+ -= "t.registers.atree[0].supply.vdd" "t.registers.atree[0].and2s[0].vdd" -= "t.registers.atree[0].supply.vss" "t.registers.atree[0].and2s[0].vss" -"t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b"->"t.registers.atree[0].and2s[0]._y"- -~("t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b")->"t.registers.atree[0].and2s[0]._y"+ -"t.registers.atree[0].and2s[0]._y"->"t.registers.atree[0].and2s[0].y"- -~("t.registers.atree[0].and2s[0]._y")->"t.registers.atree[0].and2s[0].y"+ -= "t.registers.atree[0].in[0]" "t.registers.atree[0].and2s[0].a" -= "t.registers.atree[0].in[0]" "t.registers.atree[0].tmp[0]" -= "t.registers.atree[0].in[1]" "t.registers.atree[0].and2s[0].b" -= "t.registers.atree[0].in[1]" "t.registers.atree[0].tmp[1]" -= "t.registers.atree[0].out" "t.registers.atree[0].and2s[0].y" -= "t.registers.atree[0].out" "t.registers.atree[0].tmp[2]" -= "t.registers.atree[1].supply.vdd" "t.registers.atree[1].and2s[0].vdd" -= "t.registers.atree[1].supply.vss" "t.registers.atree[1].and2s[0].vss" -"t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b"->"t.registers.atree[1].and2s[0]._y"- -~("t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b")->"t.registers.atree[1].and2s[0]._y"+ -"t.registers.atree[1].and2s[0]._y"->"t.registers.atree[1].and2s[0].y"- -~("t.registers.atree[1].and2s[0]._y")->"t.registers.atree[1].and2s[0].y"+ -= "t.registers.atree[1].in[0]" "t.registers.atree[1].and2s[0].a" -= "t.registers.atree[1].in[0]" "t.registers.atree[1].tmp[0]" -= "t.registers.atree[1].in[1]" "t.registers.atree[1].and2s[0].b" -= "t.registers.atree[1].in[1]" "t.registers.atree[1].tmp[1]" -= "t.registers.atree[1].out" "t.registers.atree[1].and2s[0].y" -= "t.registers.atree[1].out" "t.registers.atree[1].tmp[2]" -= "t.registers.atree[2].supply.vdd" "t.registers.atree[2].and2s[0].vdd" -= "t.registers.atree[2].supply.vss" "t.registers.atree[2].and2s[0].vss" -"t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b"->"t.registers.atree[2].and2s[0]._y"- -~("t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b")->"t.registers.atree[2].and2s[0]._y"+ -"t.registers.atree[2].and2s[0]._y"->"t.registers.atree[2].and2s[0].y"- -~("t.registers.atree[2].and2s[0]._y")->"t.registers.atree[2].and2s[0].y"+ -= "t.registers.atree[2].in[0]" "t.registers.atree[2].and2s[0].a" -= "t.registers.atree[2].in[0]" "t.registers.atree[2].tmp[0]" -= "t.registers.atree[2].in[1]" "t.registers.atree[2].and2s[0].b" -= "t.registers.atree[2].in[1]" "t.registers.atree[2].tmp[1]" -= "t.registers.atree[2].out" "t.registers.atree[2].and2s[0].y" -= "t.registers.atree[2].out" "t.registers.atree[2].tmp[2]" -= "t.registers.atree[3].supply.vdd" "t.registers.atree[3].and2s[0].vdd" -= "t.registers.atree[3].supply.vss" "t.registers.atree[3].and2s[0].vss" -"t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b"->"t.registers.atree[3].and2s[0]._y"- -~("t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b")->"t.registers.atree[3].and2s[0]._y"+ -"t.registers.atree[3].and2s[0]._y"->"t.registers.atree[3].and2s[0].y"- -~("t.registers.atree[3].and2s[0]._y")->"t.registers.atree[3].and2s[0].y"+ -= "t.registers.atree[3].in[0]" "t.registers.atree[3].and2s[0].a" -= "t.registers.atree[3].in[0]" "t.registers.atree[3].tmp[0]" -= "t.registers.atree[3].in[1]" "t.registers.atree[3].and2s[0].b" -= "t.registers.atree[3].in[1]" "t.registers.atree[3].tmp[1]" -= "t.registers.atree[3].out" "t.registers.atree[3].and2s[0].y" -= "t.registers.atree[3].out" "t.registers.atree[3].tmp[2]" -= "t.registers.atree[4].supply.vdd" "t.registers.atree[4].and2s[0].vdd" -= "t.registers.atree[4].supply.vss" "t.registers.atree[4].and2s[0].vss" -"t.registers.atree[4].and2s[0].a"&"t.registers.atree[4].and2s[0].b"->"t.registers.atree[4].and2s[0]._y"- -~("t.registers.atree[4].and2s[0].a"&"t.registers.atree[4].and2s[0].b")->"t.registers.atree[4].and2s[0]._y"+ -"t.registers.atree[4].and2s[0]._y"->"t.registers.atree[4].and2s[0].y"- -~("t.registers.atree[4].and2s[0]._y")->"t.registers.atree[4].and2s[0].y"+ -= "t.registers.atree[4].in[0]" "t.registers.atree[4].and2s[0].a" -= "t.registers.atree[4].in[0]" "t.registers.atree[4].tmp[0]" -= "t.registers.atree[4].in[1]" "t.registers.atree[4].and2s[0].b" -= "t.registers.atree[4].in[1]" "t.registers.atree[4].tmp[1]" -= "t.registers.atree[4].out" "t.registers.atree[4].and2s[0].y" -= "t.registers.atree[4].out" "t.registers.atree[4].tmp[2]" -= "t.registers.atree[5].supply.vdd" "t.registers.atree[5].and2s[0].vdd" -= "t.registers.atree[5].supply.vss" "t.registers.atree[5].and2s[0].vss" -"t.registers.atree[5].and2s[0].a"&"t.registers.atree[5].and2s[0].b"->"t.registers.atree[5].and2s[0]._y"- -~("t.registers.atree[5].and2s[0].a"&"t.registers.atree[5].and2s[0].b")->"t.registers.atree[5].and2s[0]._y"+ -"t.registers.atree[5].and2s[0]._y"->"t.registers.atree[5].and2s[0].y"- -~("t.registers.atree[5].and2s[0]._y")->"t.registers.atree[5].and2s[0].y"+ -= "t.registers.atree[5].in[0]" "t.registers.atree[5].and2s[0].a" -= "t.registers.atree[5].in[0]" "t.registers.atree[5].tmp[0]" -= "t.registers.atree[5].in[1]" "t.registers.atree[5].and2s[0].b" -= "t.registers.atree[5].in[1]" "t.registers.atree[5].tmp[1]" -= "t.registers.atree[5].out" "t.registers.atree[5].and2s[0].y" -= "t.registers.atree[5].out" "t.registers.atree[5].tmp[2]" -= "t.registers.atree[6].supply.vdd" "t.registers.atree[6].and2s[0].vdd" -= "t.registers.atree[6].supply.vss" "t.registers.atree[6].and2s[0].vss" -"t.registers.atree[6].and2s[0].a"&"t.registers.atree[6].and2s[0].b"->"t.registers.atree[6].and2s[0]._y"- -~("t.registers.atree[6].and2s[0].a"&"t.registers.atree[6].and2s[0].b")->"t.registers.atree[6].and2s[0]._y"+ -"t.registers.atree[6].and2s[0]._y"->"t.registers.atree[6].and2s[0].y"- -~("t.registers.atree[6].and2s[0]._y")->"t.registers.atree[6].and2s[0].y"+ -= "t.registers.atree[6].in[0]" "t.registers.atree[6].and2s[0].a" -= "t.registers.atree[6].in[0]" "t.registers.atree[6].tmp[0]" -= "t.registers.atree[6].in[1]" "t.registers.atree[6].and2s[0].b" -= "t.registers.atree[6].in[1]" "t.registers.atree[6].tmp[1]" -= "t.registers.atree[6].out" "t.registers.atree[6].and2s[0].y" -= "t.registers.atree[6].out" "t.registers.atree[6].tmp[2]" -= "t.registers.atree[7].supply.vdd" "t.registers.atree[7].and2s[0].vdd" -= "t.registers.atree[7].supply.vss" "t.registers.atree[7].and2s[0].vss" -"t.registers.atree[7].and2s[0].a"&"t.registers.atree[7].and2s[0].b"->"t.registers.atree[7].and2s[0]._y"- -~("t.registers.atree[7].and2s[0].a"&"t.registers.atree[7].and2s[0].b")->"t.registers.atree[7].and2s[0]._y"+ -"t.registers.atree[7].and2s[0]._y"->"t.registers.atree[7].and2s[0].y"- -~("t.registers.atree[7].and2s[0]._y")->"t.registers.atree[7].and2s[0].y"+ -= "t.registers.atree[7].in[0]" "t.registers.atree[7].and2s[0].a" -= "t.registers.atree[7].in[0]" "t.registers.atree[7].tmp[0]" -= "t.registers.atree[7].in[1]" "t.registers.atree[7].and2s[0].b" -= "t.registers.atree[7].in[1]" "t.registers.atree[7].tmp[1]" -= "t.registers.atree[7].out" "t.registers.atree[7].and2s[0].y" -= "t.registers.atree[7].out" "t.registers.atree[7].tmp[2]" "t.registers.clock_buffer[0].buf1.a"->"t.registers.clock_buffer[0].buf1._y"- ~("t.registers.clock_buffer[0].buf1.a")->"t.registers.clock_buffer[0].buf1._y"+ "t.registers.clock_buffer[0].buf1._y"->"t.registers.clock_buffer[0].buf1.y"- @@ -1014,49 +792,9 @@ = "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].out[1]" = "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].buf1.y" = "t.registers.clock_buffer[3].in" "t.registers.clock_buffer[3].buf1.a" -"t.registers.clock_buffer[4].buf1.a"->"t.registers.clock_buffer[4].buf1._y"- -~("t.registers.clock_buffer[4].buf1.a")->"t.registers.clock_buffer[4].buf1._y"+ -"t.registers.clock_buffer[4].buf1._y"->"t.registers.clock_buffer[4].buf1.y"- -~("t.registers.clock_buffer[4].buf1._y")->"t.registers.clock_buffer[4].buf1.y"+ -= "t.registers.clock_buffer[4].supply.vdd" "t.registers.clock_buffer[4].buf1.vdd" -= "t.registers.clock_buffer[4].supply.vss" "t.registers.clock_buffer[4].buf1.vss" -= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].out[1]" -= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].buf1.y" -= "t.registers.clock_buffer[4].in" "t.registers.clock_buffer[4].buf1.a" -"t.registers.clock_buffer[5].buf1.a"->"t.registers.clock_buffer[5].buf1._y"- -~("t.registers.clock_buffer[5].buf1.a")->"t.registers.clock_buffer[5].buf1._y"+ -"t.registers.clock_buffer[5].buf1._y"->"t.registers.clock_buffer[5].buf1.y"- -~("t.registers.clock_buffer[5].buf1._y")->"t.registers.clock_buffer[5].buf1.y"+ -= "t.registers.clock_buffer[5].supply.vdd" "t.registers.clock_buffer[5].buf1.vdd" -= "t.registers.clock_buffer[5].supply.vss" "t.registers.clock_buffer[5].buf1.vss" -= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].out[1]" -= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].buf1.y" -= "t.registers.clock_buffer[5].in" "t.registers.clock_buffer[5].buf1.a" -"t.registers.clock_buffer[6].buf1.a"->"t.registers.clock_buffer[6].buf1._y"- -~("t.registers.clock_buffer[6].buf1.a")->"t.registers.clock_buffer[6].buf1._y"+ -"t.registers.clock_buffer[6].buf1._y"->"t.registers.clock_buffer[6].buf1.y"- -~("t.registers.clock_buffer[6].buf1._y")->"t.registers.clock_buffer[6].buf1.y"+ -= "t.registers.clock_buffer[6].supply.vdd" "t.registers.clock_buffer[6].buf1.vdd" -= "t.registers.clock_buffer[6].supply.vss" "t.registers.clock_buffer[6].buf1.vss" -= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].out[1]" -= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].buf1.y" -= "t.registers.clock_buffer[6].in" "t.registers.clock_buffer[6].buf1.a" -"t.registers.clock_buffer[7].buf1.a"->"t.registers.clock_buffer[7].buf1._y"- -~("t.registers.clock_buffer[7].buf1.a")->"t.registers.clock_buffer[7].buf1._y"+ -"t.registers.clock_buffer[7].buf1._y"->"t.registers.clock_buffer[7].buf1.y"- -~("t.registers.clock_buffer[7].buf1._y")->"t.registers.clock_buffer[7].buf1.y"+ -= "t.registers.clock_buffer[7].supply.vdd" "t.registers.clock_buffer[7].buf1.vdd" -= "t.registers.clock_buffer[7].supply.vss" "t.registers.clock_buffer[7].buf1.vss" -= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]" -= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].buf1.y" -= "t.registers.clock_buffer[7].in" "t.registers.clock_buffer[7].buf1.a" = "t.registers._in_v_temp" "t.registers.clk_dly.in" = "t.registers._in_v_temp" "t.registers.val_input_X.in" = "t.registers._in_v_temp" "t.registers.val_input.out" -= "t.registers._clock" "t.registers.and_encoder[7].b" -= "t.registers._clock" "t.registers.and_encoder[6].b" -= "t.registers._clock" "t.registers.and_encoder[5].b" -= "t.registers._clock" "t.registers.and_encoder[4].b" = "t.registers._clock" "t.registers.and_encoder[3].b" = "t.registers._clock" "t.registers.and_encoder[2].b" = "t.registers._clock" "t.registers.and_encoder[1].b" diff --git a/test/unit_tests/register_write/test.act b/test/unit_tests/register_write/test.act index 44c41da..c061169 100644 --- a/test/unit_tests/register_write/test.act +++ b/test/unit_tests/register_write/test.act @@ -31,7 +31,7 @@ import globals; open tmpl::dataflow_neuro; // 2 bits encoder, 2 bits long words, 2 delays???? -defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){ +defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){ register_rw<2,2,2> registers(.in=in,.data = data); //Low active Reset diff --git a/test/unit_tests/register_write/test.prsim b/test/unit_tests/register_write/test.prsim index 09d42e8..722f651 100644 --- a/test/unit_tests/register_write/test.prsim +++ b/test/unit_tests/register_write/test.prsim @@ -1,13 +1,12 @@ watchall system "echo '[0] start test'" -set Reset 1 - set-qdi-channel-neutral "t.in" 5 set t.data[0].d[0] 0 set t.data[0].d[1] 0 set t.data[1].d[0] 0 set t.data[1].d[1] 0 +set Reset 0 cycle status X mode run @@ -16,7 +15,6 @@ assert t.data[0].d[0] 0 assert t.data[0].d[1] 0 assert t.data[1].d[0] 0 assert t.data[1].d[1] 0 -set Reset 0 cycle system "echo '[1] reset completed'" # Set delay config lines @@ -28,14 +26,15 @@ system "echo '[2] delay line set'" set-qdi-channel-valid "t.in" 5 3 cycle assert-qdi-channel-valid "t.in" 5 3 -assert t.registers._clock 1 +assert t.registers._clock 0 assert t.registers._out_encoder[0] 1 assert t.registers._out_encoder[1] 0 assert t.registers._out_encoder[2] 0 assert t.registers._out_encoder[3] 0 +cycle set-qdi-channel-neutral "t.in" 5 cycle -assert t.registers._clock 0 +assert t.registers._clock 1 assert t.registers.ff[0].q 1 assert t.registers.ff[1].q 1 system "echo '[3] clock checked'"