From ea3f91d6deae2f81b1211eff55f75ae4d73a24c9 Mon Sep 17 00:00:00 2001 From: alexmadison Date: Mon, 4 Apr 2022 17:14:08 +0200 Subject: [PATCH] chips init --- dataflow_neuro/chips.act | 149 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 dataflow_neuro/chips.act diff --git a/dataflow_neuro/chips.act b/dataflow_neuro/chips.act new file mode 100644 index 0000000..fe201f5 --- /dev/null +++ b/dataflow_neuro/chips.act @@ -0,0 +1,149 @@ +/************************************************************************* + * + * This file is part of ACT dataflow neuro library + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + + +import "../../dataflow_neuro/cell_lib_async.act"; +import "../../dataflow_neuro/cell_lib_std.act"; +import "../../dataflow_neuro/treegates.act"; +import "../../dataflow_neuro/primitives.act"; +import "../../dataflow_neuro/coders.act"; +// import tmpl::dataflow_neuro; +// import tmpl::dataflow_neuro; +import std::channel; +open std::channel; + + +/************************************************************************* + * + * This file is part of ACT dataflow neuro library + * + * Copyright (c) 2022 University of Groningen - Ole Richter + * Copyright (c) 2022 University of Groningen - Michele Mastella + * Copyright (c) 2022 University of Groningen - Hugh Greatorex + * Copyright (c) 2022 University of Groningen - Madison Cotteret + * + * + * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later + * + * You may redistribute and modify this documentation and make products + * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). + * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY + * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 + * for applicable conditions. + * + * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro + * + * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on + * these sources, You must maintain the Source Location visible in its + * documentation. + * + ************************************************************************** + */ + + +import "../../dataflow_neuro/cell_lib_async.act"; +import "../../dataflow_neuro/cell_lib_std.act"; +import "../../dataflow_neuro/treegates.act"; +import "../../dataflow_neuro/primitives.act"; +import "../../dataflow_neuro/registers.act"; +import "../../dataflow_neuro/coders.act"; +// import tmpl::dataflow_neuro; +// import tmpl::dataflow_neuro; +import std::channel; +open std::channel; + +namespace tmpl { + namespace dataflow_neuro { + +export template + +defproc chip_texel (bd in, out; + Mx1of2 reg_data[REG_M]; + a1of1 synapses[N_SYN_X * N_SYN_Y]; + a1of1 neurons[N_NRN_X * N_NRN_Y]; + bool? bd_dly_cfg[N_BD_DLY_CFG]; + bool? loopback_en; + power supply; + bool? reset_B){ + + bd2qdi _bd2qdi(.in = in, .supply = supply); + fifo fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply); + + fork _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply); + + // Loopback + fifo fifo_fork2drop(.in = _fork.out1, .reset_B = reset_B, .supply = supply); + dropper_static _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en, + .supply = supply); + + // Onwards + fifo fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply); + demux_msb _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply); + + // Register + fifo fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply); + registerA_wr_array register(.in = fifo_dmx2reg.out, .data = reg_data, + .supply = supply, .reset_B = reset_B); + + // TO ADD: nrn/syn mon decoders + + // Decoder + // slice_data + fifo fifo_dmx2dec(.in = _demux.out, .reset_B = reset_B, .supply = supply); + decoder_2d_hybrid decoder(.in = fifo_dmx2dec.in, + .out = synapses, + .hs_en = register.data[0].d[0].f, // Defaults to handshake disable + .supply = supply, .reset_B = reset_B) + + + + + + + + + + + + + + + + +} +} +} +