From f5859040d81245fb6dbadcd41de128bf18f7bf06 Mon Sep 17 00:00:00 2001
From: Michele <michelemastella27@gmail.com>
Date: Thu, 3 Mar 2022 12:00:49 +0100
Subject: [PATCH] Arbiter tree test

---
 .../unit_tests/arbiter_tree_test/run/test.prs |  3 +
 test/unit_tests/arbiter_tree_test/test.act    | 62 ++++++++++++++++++
 test/unit_tests/arbiter_tree_test/test.prsim  | 64 +++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 test/unit_tests/arbiter_tree_test/run/test.prs
 create mode 100644 test/unit_tests/arbiter_tree_test/test.act
 create mode 100644 test/unit_tests/arbiter_tree_test/test.prsim

diff --git a/test/unit_tests/arbiter_tree_test/run/test.prs b/test/unit_tests/arbiter_tree_test/run/test.prs
new file mode 100644
index 0000000..02d06ef
--- /dev/null
+++ b/test/unit_tests/arbiter_tree_test/run/test.prs
@@ -0,0 +1,3 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
diff --git a/test/unit_tests/arbiter_tree_test/test.act b/test/unit_tests/arbiter_tree_test/test.act
new file mode 100644
index 0000000..249aa2d
--- /dev/null
+++ b/test/unit_tests/arbiter_tree_test/test.act
@@ -0,0 +1,62 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+
+defproc arbiter_treee (a1of1 in[5]; a1of1 out)
+{
+    a1of1 _in[5];
+    power _supply
+    _supply.vdd = Vdd;
+    _supply.vss = GND;
+
+    fifo_t<2> fifo_to_tree[5];
+    (i:5:
+        fifo_to_tree[i].in = in[i];
+        fifo_to_tree[i].out = _in[i];
+        fifo_to_tree.supply = _supply;
+        fifo_to_tree.reset_B = _reset_B;
+    )
+
+    arbiter_tree<5> at_cell(.in=_in, .out = out);
+
+    //Low active Reset
+    bool _reset_B;
+    prs {
+        Reset => _reset_B-
+    }
+
+    at_cell.supply = _supply;
+    
+}
+
+arbiter_treee my_tree;
diff --git a/test/unit_tests/arbiter_tree_test/test.prsim b/test/unit_tests/arbiter_tree_test/test.prsim
new file mode 100644
index 0000000..65294dd
--- /dev/null
+++ b/test/unit_tests/arbiter_tree_test/test.prsim
@@ -0,0 +1,64 @@
+
+watchall
+set Reset 1
+set my_tree.in[0].r 0
+set my_tree.in[1].r 0
+set my_tree.in[2].r 0
+set my_tree.in[3].r 0
+set my_tree.in[4].r 0
+set my_tree.out.a 0
+
+cycle
+
+assert my_tree.in[0].a 0
+assert my_tree.in[1].a 0
+assert my_tree.in[2].a 0
+assert my_tree.in[3].a 0
+assert my_tree.in[4].a 0
+assert my_tree.out.r 0
+
+system "echo '-------------------------------------------------'"
+system "echo '[0] System initialized'"
+
+set Reset 0
+cycle
+system "echo '-------------------------------------------------'"
+system "echo '[1] System reset completed'"
+
+set in[0].r 1
+set in[2].r 1
+set in[4].r 1
+
+cycle
+
+assert out.r 1
+set out.a 1
+cycle
+
+assert out.r 0
+set out.a 0
+
+cycle
+
+assert out.r 1
+set out.a 1
+cycle
+
+assert out.r 0
+set out.a 0
+
+cycle
+
+assert out.r 1
+set out.a 1
+cycle
+
+assert out.r 0
+set out.a 0
+
+cycle
+
+
+system "echo '-------------------------------------------------'"
+system "echo '[3] Sent three inputs, received 3 outputs'"
+