/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library.
 * It's the testing facility for cell_lib_std.act
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter  
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */

import "../../dataflow_neuro/registers.act";
import globals;

open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){

    register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
    //Low active Reset 
    bool _reset_B; 
    power _supply;
    prs {
    	Reset => _reset_B-
    }
    registers.supply = _supply;
    _supply.vss = GND;
    _supply.vdd = Vdd;
    registers.reset_B = _reset_B;
    registers.reset_mem_B = _reset_B;
    registers.dly_cfg = dly_cfg;
    
}

register_test t;