/************************************************************************* * * This file is part of ACT dataflow neuro library * * Copyright (c) 2022 University of Groningen - Ole Richter * Copyright (c) 2022 University of Groningen - Michele Mastella * Copyright (c) 2022 University of Groningen - Hugh Greatorex * * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * * You may redistribute and modify this documentation and make products * using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl). * This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED * WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY * AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 * for applicable conditions. * * Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro * * As per CERN-OHL-W v2 section 4.1, should You produce hardware based on * these sources, You must maintain the Source Location visible in its * documentation. * ************************************************************************** */ import "../../dataflow_neuro/cell_lib_async.act"; import "../../dataflow_neuro/cell_lib_std.act"; import "../../dataflow_neuro/treegates.act"; // import tmpl::dataflow_neuro; // import tmpl::dataflow_neuro; import std::channel; open std::channel; namespace tmpl { namespace dataflow_neuro { // @ole talk to rajit, we use valid the wrong way arround according to stdlib template defchan gen_avMx1of2 <: chan(int) (std::data::Mx1of2?! d; bool!? a; bool!? v) { { 0 <= V & std::ceil_log2(V) < M : "Initial token value out of range" }; methods { /*-- initialize channel, sender end --*/ send_init { [ reset -> (,i:M: [ ((V >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v] [] else -> (,i:M: d.d[i].t-,d.d[i].f-);[~v] ] } /*-- set output data --*/ set { (,i:M: [((self >> i) & 1) = 0 -> d.d[i].f+ [] else -> d.d[i].t+ ]);[v] } /*-- finish synchronization --*/ send_up { [a] } /*-- reset part of the protocol --*/ send_rest { (,i:M: d.d[i].t-,d.d[i].f-);[~v],[~a] } /*-- initialize channel, receiver end --*/ recv_init { v-;a- } /*-- get value --*/ get { [(&i:M: d.d[i].t | d.d[i].f)]; self := 0; (;i:M: [ d.d[i].t -> self := self | (1 << i) [] else -> skip ] ) } /*-- finish synchronization action --*/ recv_up { v+,a+ } /*-- reset part of the protocol --*/ recv_rest { [(&i:M:~d.d[i].t & ~d.d[i].f)];v-,a- } /*-- probe expression on receiver --*/ // i think this deadlocks with recv_up recv_probe = v; // no sender probe } } export defchan avMx1of2 <: gen_avMx1of2 () { } export defchan avrMx1of2 <: gen_avMx1of2 () { } /** * the buffer template gives you a standart buffer of bitwidth N * */ export template defproc buffer (avMx1of2 in; avMx1of2 out; bool? reset_B; power supply) { //control bool _en, _reset_BX,_reset_BXX[N]; A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); //validity bool _in_v; ctree vc(.in=in.d,.out=_in_v,.supply=supply); BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); //function bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N]; A_2C1N_RB_X4 f_buf_func[N]; A_2C1N_RB_X4 t_buf_func[N]; sigbuf en_buf_t(.in=_en, .out=_en_X_t, .supply=supply); sigbuf en_buf_f(.in=_en, .out=_en_X_f, .supply=supply); INV_X1 out_a_inv(.a=out.a,.y=_out_a_B); sigbuf out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t); sigbuf out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f); // check if you can also do single var to array connect a=b[N] // and remove them from the loop (i:N: f_buf_func[i].y=out.d.d[i].f; t_buf_func[i].y=out.d.d[i].t; f_buf_func[i].c1=_en_X_f[i]; t_buf_func[i].c1=_en_X_t[i]; f_buf_func[i].c2=_out_a_BX_f[i]; t_buf_func[i].c2=_out_a_BX_t[i]; f_buf_func[i].n1=in.d.d[i].f; t_buf_func[i].n1=in.d.d[i].t; f_buf_func[i].vdd=supply.vdd; t_buf_func[i].vdd=supply.vdd; f_buf_func[i].vss=supply.vss; t_buf_func[i].vss=supply.vss; t_buf_func[i].pr_B = _reset_BXX[i]; t_buf_func[i].sr_B = _reset_BXX[i]; f_buf_func[i].pr_B = _reset_BXX[i]; f_buf_func[i].sr_B = _reset_BXX[i]; ) } // export template // defproc demux (avMx1of2 in; avMx1of2 out1; avMx1of2 out2; bool? reset_B, c_t, c_f; power supply) { // //control // bool _en, _reset_BX,_reset_BXX[N], _out_v; // OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss); // A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss); // A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); // BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); // sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); // A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); // //validity // bool _in_v, _c_f_buf, _c_t_buf, _c_v, _in_c_v_; // sigbuf c_buf_t(.in=c_t, .out=_c_t_buf); // sigbuf c_buf_f(.in=c_f, .out=_c_f_buf); // OR2_X1 c_f_c_t_or(.a=c_t, .b=c_f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss); // ctree vc(.in=in.d,.out=_in_v,.supply=supply); // A_2C_RB_X4 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss); // BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); // //function // //func buffer out1 // bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N]; // A_2C2N_RB_X4 out1_f_buf_func[N]; // A_2C2N_RB_X4 out1_t_buf_func[N]; // sigbuf out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply); // sigbuf out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply); // INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B); // sigbuf out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t); // sigbuf out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f); // (i:N: // out1_f_buf_func[i].y=out1.d.d[i].f; // out1_t_buf_func[i].y=out1.d.d[i].t; // out1_f_buf_func[i].c1=_en1_X_f[i]; // out1_t_buf_func[i].c1=_en1_X_t[i]; // out1_f_buf_func[i].c2=_out1_a_BX_f[i]; // out1_t_buf_func[i].c2=_out1_a_BX_t[i]; // out1_f_buf_func[i].n1=in.d.d[i].f; // out1_t_buf_func[i].n1=in.d.d[i].t; // out1_f_buf_func[i].vdd=supply.vdd; // out1_t_buf_func[i].vdd=supply.vdd; // out1_f_buf_func[i].vss=supply.vss; // out1_t_buf_func[i].vss=supply.vss; // out1_t_buf_func[i].pr_B = _reset_BXX[i]; // out1_t_buf_func[i].sr_B = _reset_BXX[i]; // out1_f_buf_func[i].pr_B = _reset_BXX[i]; // out1_f_buf_func[i].sr_B = _reset_BXX[i]; // out1_f_buf_func[i].n2=_c_t_buf; // out1_t_buf_func[i].n2=_c_t_buf; // ) // //func buffer out2 // bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N]; // A_2C2N_RB_X4 out2_f_buf_func[N]; // A_2C2N_RB_X4 out2_t_buf_func[N]; // sigbuf out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply); // sigbuf out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply); // INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B); // sigbuf out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t); // sigbuf out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f); // (i:N: // out2_f_buf_func[i].y=out2.d.d[i].f; // out2_t_buf_func[i].y=out2.d.d[i].t; // out2_f_buf_func[i].c1=_en2_X_f[i]; // out2_t_buf_func[i].c1=_en2_X_t[i]; // out2_f_buf_func[i].c2=_out2_a_BX_f[i]; // out2_t_buf_func[i].c2=_out2_a_BX_t[i]; // out2_f_buf_func[i].n1=in.d.d[i].f; // out2_t_buf_func[i].n1=in.d.d[i].t; // out2_f_buf_func[i].vdd=supply.vdd; // out2_t_buf_func[i].vdd=supply.vdd; // out2_f_buf_func[i].vss=supply.vss; // out2_t_buf_func[i].vss=supply.vss; // out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1]; // out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1]; // out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1]; // out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1]; // out2_f_buf_func[i].n2=_c_f_buf; // out2_t_buf_func[i].n2=_c_f_buf; // ) // } export template defproc fork (avMx1of2 in; avMx1of2 out1; avMx1of2 out2 ; bool? reset_B; power supply) { // control bool _en, _reset_BX,_reset_BXX[N*2]; A_4C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out1.v,.c4=out2.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); A_1C2P_X1 en_ctl(.c1=in.a,.p1=out1.v,.p2=out2.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss); //reset_buffers BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); //validity bool _in_v; ctree vc(.in=in.d,.out=_in_v,.supply=supply); BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss); //function //func buffer out1 bool _out1_a_BX_t[N],_out1_a_BX_f[N],_out1_a_B,_en1_X_t[N],_en1_X_f[N]; A_2C1N_RB_X4 out1_f_buf_func[N]; A_2C1N_RB_X4 out1_t_buf_func[N]; sigbuf out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply); sigbuf out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply); INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B); sigbuf out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t); sigbuf out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f); (i:N: out1_f_buf_func[i].y=out1.d.d[i].f; out1_t_buf_func[i].y=out1.d.d[i].t; out1_f_buf_func[i].c1=_en1_X_f[i]; out1_t_buf_func[i].c1=_en1_X_t[i]; out1_f_buf_func[i].c2=_out1_a_BX_f[i]; out1_t_buf_func[i].c2=_out1_a_BX_t[i]; out1_f_buf_func[i].n1=in.d.d[i].f; out1_t_buf_func[i].n1=in.d.d[i].t; out1_f_buf_func[i].vdd=supply.vdd; out1_t_buf_func[i].vdd=supply.vdd; out1_f_buf_func[i].vss=supply.vss; out1_t_buf_func[i].vss=supply.vss; out1_t_buf_func[i].pr_B = _reset_BXX[i]; out1_t_buf_func[i].sr_B = _reset_BXX[i]; out1_f_buf_func[i].pr_B = _reset_BXX[i]; out1_f_buf_func[i].sr_B = _reset_BXX[i]; ) //func buffer out2 bool _out2_a_BX_t[N],_out2_a_BX_f[N],_out2_a_B,_en2_X_t[N],_en2_X_f[N]; A_2C1N_RB_X4 out2_f_buf_func[N]; A_2C1N_RB_X4 out2_t_buf_func[N]; sigbuf out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply); sigbuf out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply); INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B); sigbuf out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t); sigbuf out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f); (i:N: out2_f_buf_func[i].y=out2.d.d[i].f; out2_t_buf_func[i].y=out2.d.d[i].t; out2_f_buf_func[i].c1=_en2_X_f[i]; out2_t_buf_func[i].c1=_en2_X_t[i]; out2_f_buf_func[i].c2=_out2_a_BX_f[i]; out2_t_buf_func[i].c2=_out2_a_BX_t[i]; out2_f_buf_func[i].n1=in.d.d[i].f; out2_t_buf_func[i].n1=in.d.d[i].t; out2_f_buf_func[i].vdd=supply.vdd; out2_t_buf_func[i].vdd=supply.vdd; out2_f_buf_func[i].vss=supply.vss; out2_t_buf_func[i].vss=supply.vss; out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1]; out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1]; out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1]; out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1]; ) } // export template // defproc merge (avMx1of2 in1; avMx1of2 in2; avMx1of2 out ; bool? reset_B; power supply) { // //control // bool _en, _reset_BX,_reset_BXX[N]; // A_4C_RB_X4 in1ack_ctl(.c1=in1arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); // A_4C_RB_X4 in2ack_ctl(.c1=in2arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); // A_4P_1N1N en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out_a_X,.p4 = out.v, .n1 = in1.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss); // //reset_buffers // BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); // sigbuf reset_bufarray(.in=_reset_BX, .out=_reset_BXX); // //validity // bool _in1_v,_in2_v; // a1of1 _in1_temp,_in2_temp,_out_temp; // ctree vc1(.in=in1.d,.out=in1.v,.supply=supply); // ctree vc2(.in=in2.d,.out=in2.v,.supply=supply); // arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp) // _in1_temp.r = in1.v // _in2_temp.r = in2.v // _in1_temp.a = // _in1_temp.a = // _out_temp.r = _out_temp.a //function // } export defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply) { bool _y1_arb,_y2_arb; A_2C_B_X1 ack_cel1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss); A_2C_B_X1 ack_cel2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss); OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss); ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss); } }}