module tmpl_0_0dataflow__neuro_0_0fifo_35_75_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   
   input Iout_a ;
   input Iout_v ;
   input reset_B;

// -- signals ---
   wire Ififo_element1_in_d_d1_d0 ;
   wire Ififo_element4_in_d_d4_d1 ;
   wire Ififo_element4_in_d_d1_d1 ;
   wire Ififo_element2_in_d_d4_d1 ;
   wire Ififo_element2_in_d_d2_d0 ;
   output Iin_a ;
   wire Iout_a ;
   output Iout_d_d2_d1 ;
   wire Ififo_element4_in_d_d2_d0 ;
   wire Ififo_element4_in_d_d0_d1 ;
   wire Ififo_element1_in_d_d3_d1 ;
   wire Ififo_element4_in_d_d3_d0 ;
   wire Ififo_element2_in_d_d0_d1 ;
   wire Ififo_element3_in_d_d4_d1 ;
   wire Ififo_element2_in_v ;
   wire Ififo_element2_in_d_d1_d0 ;
   wire Ififo_element1_in_d_d4_d0 ;
   wire Iin_d_d4_d1 ;
   wire reset_B;
   wire Ififo_element4_in_d_d2_d1 ;
   output Iout_d_d3_d1 ;
   wire Ififo_element2_in_d_d0_d0 ;
   output Iout_d_d4_d1 ;
   wire Ififo_element2_in_d_d3_d1 ;
   wire Iin_d_d1_d1 ;
   wire _reset_BX ;
   output Iout_d_d1_d1 ;
   wire Ififo_element2_in_a ;
   wire Ififo_element1_in_v ;
   wire Iin_d_d2_d0 ;
   wire Ififo_element3_in_d_d4_d0 ;
   wire Ififo_element2_in_d_d4_d0 ;
   wire Ififo_element3_in_d_d0_d1 ;
   wire Ififo_element2_in_d_d2_d1 ;
   wire Ififo_element1_in_a ;
   wire Iin_d_d2_d1 ;
   wire Ififo_element1_in_d_d3_d0 ;
   wire Iin_d_d0_d1 ;
   wire Iin_d_d3_d1 ;
   output Iout_d_d4_d0 ;
   wire Ififo_element3_in_d_d3_d1 ;
   wire Ififo_element3_in_d_d1_d0 ;
   wire Iin_d_d4_d0 ;
   wire Ififo_element3_in_a ;
   wire Ififo_element2_in_d_d3_d0 ;
   output Iout_d_d0_d0 ;
   wire Ififo_element4_in_d_d4_d0 ;
   wire Iout_v ;
   output Iout_d_d2_d0 ;
   output Iout_d_d1_d0 ;
   wire Ififo_element4_in_d_d0_d0 ;
   wire Iin_d_d3_d0 ;
   wire I_reset_BXX4 ;
   wire Ififo_element3_in_d_d2_d0 ;
   wire Ififo_element3_in_d_d1_d1 ;
   wire Iin_d_d0_d0 ;
   wire Ififo_element4_in_v ;
   wire Ififo_element3_in_d_d3_d0 ;
   wire Ififo_element1_in_d_d2_d1 ;
   wire Ififo_element1_in_d_d2_d0 ;
   wire Ififo_element1_in_d_d0_d1 ;
   output Iin_v ;
   wire Ififo_element4_in_d_d1_d0 ;
   wire Ififo_element2_in_d_d1_d1 ;
   wire Ififo_element1_in_d_d0_d0 ;
   wire Ififo_element3_in_v ;
   wire Ififo_element1_in_d_d4_d1 ;
   wire Ififo_element3_in_d_d2_d1 ;
   wire Ififo_element3_in_d_d0_d0 ;
   output Iout_d_d3_d0 ;
   wire Ififo_element4_in_a ;
   output Iout_d_d0_d1 ;
   wire Ififo_element4_in_d_d3_d1 ;
   wire Ififo_element1_in_d_d1_d1 ;
   wire Iin_d_d1_d0 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_35_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX4 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element0  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iout_a (Ififo_element1_in_a ), .Iout_v (Ififo_element1_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element1  (.Iin_d_d0_d0 (Ififo_element1_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element1_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element1_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element1_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element1_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element1_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element1_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element1_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element1_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element1_in_d_d4_d1 ), .Iin_a (Ififo_element1_in_a ), .Iin_v (Ififo_element1_in_v ), .Iout_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iout_a (Ififo_element2_in_a ), .Iout_v (Ififo_element2_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element2  (.Iin_d_d0_d0 (Ififo_element2_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element2_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element2_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element2_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element2_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element2_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element2_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element2_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element2_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element2_in_d_d4_d1 ), .Iin_a (Ififo_element2_in_a ), .Iin_v (Ififo_element2_in_v ), .Iout_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iout_a (Ififo_element3_in_a ), .Iout_v (Ififo_element3_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element3  (.Iin_d_d0_d0 (Ififo_element3_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element3_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element3_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element3_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element3_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element3_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element3_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element3_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element3_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element3_in_d_d4_d1 ), .Iin_a (Ififo_element3_in_a ), .Iin_v (Ififo_element3_in_v ), .Iout_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iout_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iout_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iout_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iout_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iout_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iout_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iout_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iout_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iout_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iout_a (Ififo_element4_in_a ), .Iout_v (Ififo_element4_in_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ififo_element4  (.Iin_d_d0_d0 (Ififo_element4_in_d_d0_d0 ), .Iin_d_d0_d1 (Ififo_element4_in_d_d0_d1 ), .Iin_d_d1_d0 (Ififo_element4_in_d_d1_d0 ), .Iin_d_d1_d1 (Ififo_element4_in_d_d1_d1 ), .Iin_d_d2_d0 (Ififo_element4_in_d_d2_d0 ), .Iin_d_d2_d1 (Ififo_element4_in_d_d2_d1 ), .Iin_d_d3_d0 (Ififo_element4_in_d_d3_d0 ), .Iin_d_d3_d1 (Ififo_element4_in_d_d3_d1 ), .Iin_d_d4_d0 (Ififo_element4_in_d_d4_d0 ), .Iin_d_d4_d1 (Ififo_element4_in_d_d4_d1 ), .Iin_a (Ififo_element4_in_a ), .Iin_v (Ififo_element4_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(I_reset_BXX4 ), .vdd(vdd), .vss(vss));
endmodule