module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss); 
   input vdd;
   input vss;
   input Iin0 ;
   input Iin1 ;
   input Iin2 ;
   input Iin3 ;
   input Iin4 ;
   input Iin5 ;
   input Iin6 ;
   input Iin7 ;
   input Iin8 ;
   output out;

// -- signals ---
   wire Iin3 ;
   wire Iin2 ;
   wire Iin6 ;
   wire Itmp10 ;
   wire Iin1 ;
   wire Itmp13 ;
   wire Iin8 ;
   wire Iin7 ;
   wire Iin4 ;
   wire Itmp12 ;
   wire Iin5 ;
   wire Itmp9 ;
   wire Itmp11 ;
   wire Iin0 ;
   wire out ;
   wire Itmp14 ;

// --- instances
A_2C_B_X1 IC2Els0  (.y(Itmp9 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els1  (.y(Itmp10 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els2  (.y(Itmp11 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els3  (.y(Itmp13 ), .c1(Itmp9 ), .c2(Itmp10 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els4  (.y(Itmp14 ), .c1(Itmp11 ), .c2(Itmp12 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 IC2Els5  (.y(out), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
A_3C_B_X1 IC3Els0  (.y(Itmp12 ), .c1(Iin6 ), .c2(Iin7 ), .c3(Iin8 ), .vdd(vdd), .vss(vss));
endmodule