/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library.
 * It's the testing facility for cell_lib_std.act
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter  
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */

import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/interfaces.act";

import globals;
import std::data;

open std::data;

open tmpl::dataflow_neuro;

defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]; bool? dly_cfg2[2]){
    bool _reset_B; 
    prs {
        Reset => _reset_B-
    }
    power supply;
    supply.vdd = Vdd;
    supply.vss = GND;

    bd2qdi<9,4,2> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2, .reset_B = _reset_B, .supply = supply);

    fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);

    // Make a register array with 3 bit address (-> 8 registers), 
    // each register holding 5 bits.
    register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
        .reset_B = _reset_B, .supply = supply);

    fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);

    qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
}


// fifo_decoder_neurons_encoder_fifo e;
fifo_reg_fifo_3x5x8 b;