module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , vdd, vss); 
   input vdd;
   input vss;
   input Iin_d0_d0 ;
   input Iin_d0_d1 ;
   input Iin_d1_d0 ;
   input Iin_d1_d1 ;
   input Iin_d2_d0 ;
   input Iin_d2_d1 ;
   input en;
   
   
   
   
   
   

// -- signals ---
   wire Isb_en_out0 ;
   wire Iin_d2_d0 ;
   wire Idecoder_final_refresh_d0_d1 ;
   wire Idecoder_final_refresh_d0_d0 ;
   output Iout5 ;
   wire Idecoder_final_refresh_d2_d0 ;
   wire Ien_ands_t2_y ;
   wire Idecoder_final_refresh_d1_d0 ;
   output Iout4 ;
   wire Ien_ands_t0_y ;
   wire Iin_d0_d0 ;
   output Iout2 ;
   wire Idecoder_final_refresh_d1_d1 ;
   output Iout0 ;
   wire Ien_ands_f2_y ;
   wire Ien_ands_t1_y ;
   wire Ien_ands_f1_y ;
   output Iout3 ;
   wire Iin_d2_d1 ;
   wire Idecoder_final_refresh_d2_d1 ;
   wire Iin_d1_d0 ;
   wire en;
   output Iout1 ;
   wire Iin_d1_d1 ;
   wire Iin_d0_d1 ;
   wire Ien_ands_f0_y ;

// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder  (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Isb_en  (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t0  (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t1  (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t2  (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f0  (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f1  (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f2  (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
endmodule