module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , vdd, vss); 
   input vdd;
   input vss;
   input Iin_d0_d0 ;
   input Iin_d0_d1 ;
   input Iin_d1_d0 ;
   input Iin_d1_d1 ;
   input Iin_d2_d0 ;
   input Iin_d2_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   

// -- signals ---
   wire Iin_d1_d0 ;
   output Iout0 ;
   wire Iin_d2_d1 ;
   output Iout4 ;
   output Ifinal_refresh_d2_d0 ;
   wire Iin_d1_d1 ;
   output Iout2 ;
   output Ifinal_refresh_d0_d0 ;
   output Ifinal_refresh_d1_d1 ;
   output Ifinal_refresh_d1_d0 ;
   wire Iin_d0_d0 ;
   output Iout3 ;
   wire Iin_d2_d0 ;
   wire Iin_d0_d1 ;
   output Iout5 ;
   output Iout1 ;
   output Ifinal_refresh_d2_d1 ;
   output Ifinal_refresh_d0_d1 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree0  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree1  (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree2  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree3  (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree4  (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree5  (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_tX0  (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_tX1  (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_tX2  (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_fX0  (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_fX1  (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
BUF_X12 Iin_fX2  (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
endmodule