module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss); 
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Iout_a ;
   input Iout_v ;
   input reset_B;

// -- signals ---
   output Iout_d_d1_d0 ;
   wire _reset_BX ;
   wire Iin_d_d6_d1 ;
   wire Iout_v ;
   wire Iin_d_d1_d0 ;
   wire Iin_d_d0_d0 ;
   output Iout_d_d3_d0 ;
   output Iout_d_d2_d0 ;
   output Iin_a ;
   output Iout_d_d5_d1 ;
   output Iout_d_d2_d1 ;
   output Iout_d_d1_d1 ;
   wire reset_B;
   output Iout_d_d4_d1 ;
   output Iout_d_d3_d1 ;
   wire Iin_d_d3_d1 ;
   wire _en ;
   wire Iin_d_d5_d0 ;
   wire Iin_d_d2_d0 ;
   wire Iin_d_d2_d1 ;
   output Iout_d_d5_d0 ;
   output Iout_d_d4_d0 ;
   wire Iin_d_d0_d1 ;
   wire I_out_a_BX0 ;
   output Iout_d_d0_d1 ;
   wire Iout_a ;
   wire Ien_buf_out0 ;
   output Iin_v ;
   output Iout_d_d6_d0 ;
   wire I_reset_BXX0 ;
   wire _in_v ;
   output Iout_d_d0_d0 ;
   wire Iin_d_d5_d1 ;
   wire Iin_d_d4_d1 ;
   wire Iin_d_d4_d0 ;
   wire Iin_d_d1_d1 ;
   wire Iin_d_d3_d0 ;
   output Iout_d_d6_d1 ;
   wire Iin_d_d6_d0 ;
   wire _out_a_B ;

// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf  (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 Iinack_ctl  (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ireset_bufarray  (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
BUF_X4 Iin_v_buf  (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 Iout_a_inv  (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Ivc  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
A_1C1P_X1 Ien_ctl  (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ien_buf  (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
BUF_X1 Ireset_buf  (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func0  (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func1  (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func2  (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func3  (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func4  (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func5  (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 It_buf_func6  (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func0  (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func1  (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func2  (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func3  (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func4  (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func5  (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 If_buf_func6  (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
endmodule