module tmpl_0_0dataflow__neuro_0_0delay__chain_33_4(out, in, vdd, vss); 
   input vdd;
   input vss;
   output out;
   input in;

// -- signals ---
   wire Idly1_a ;
   wire out ;
   wire Idly2_a ;
   wire in;

// --- instances
DLY4_X1 Idly0  (.y(Idly1_a ), .a(in), .vdd(vdd), .vss(vss));
DLY4_X1 Idly1  (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
DLY4_X1 Idly2  (.y(out), .a(Idly2_a ), .vdd(vdd), .vss(vss));
endmodule