module tmpl_0_0dataflow__neuro_0_0vtree_34_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , out, vdd, vss); 
   input vdd;
   input vss;
   input Iin_d0_d0 ;
   input Iin_d0_d1 ;
   input Iin_d1_d0 ;
   input Iin_d1_d1 ;
   input Iin_d2_d0 ;
   input Iin_d2_d1 ;
   input Iin_d3_d0 ;
   input Iin_d3_d1 ;
   output out;

// -- signals ---
   wire Iin_d2_d0 ;
   wire Iin_d0_d0 ;
   wire out ;
   wire Iin_d1_d1 ;
   wire Iin_d3_d1 ;
   wire Ict_in0 ;
   wire Iin_d1_d0 ;
   wire Ict_in2 ;
   wire Iin_d3_d0 ;
   wire Ict_in1 ;
   wire Iin_d0_d1 ;
   wire Iin_d2_d1 ;
   wire Ict_in3 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0ctree_34_4 Ict  (.Iin0 (Ict_in0 ), .Iin1 (Ict_in1 ), .Iin2 (Ict_in2 ), .Iin3 (Ict_in3 ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf0  (.y(Ict_in0 ), .a(Iin_d0_d1 ), .b(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf1  (.y(Ict_in1 ), .a(Iin_d1_d1 ), .b(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf2  (.y(Ict_in2 ), .a(Iin_d2_d1 ), .b(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf3  (.y(Ict_in3 ), .a(Iin_d3_d1 ), .b(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
endmodule